We propose the use of Ge-cap quantum-well (QW) bulk FinFET for 5 nm CMOS integration, which is a Si channel wrapped with Ge around three sides of the fin channel. The simulation results show that the Ge-cap FinFET structure demonstrates better performance than pure Si, pure Ge, and Si-cap FinFET structures. By optimizing Si fin width and Ge-cap thickness, the on-state current of nFET and pFET can also be symmetric without changing the total fin width (F Wp = F Wn ). The electrons in Ge-cap nFinFET concentrate in the Si channel because of QWs formed in the lowest conduction band of the Ge and Si heterostructure, while the holes in Ge-cap pFinFET prefer to stay in Ge surfaces owing to QWs formed in the Ge valence band. The physics studies of this device have made the design rules relevant for the application of the CMOS inverter and static random access memory (SRAM) application technology.
As technology develops, the stacked nanosheet (NS) structure demonstrates promise for use in future technology nodes. This study demonstrated the excellent performance of stacked-NS channels with junctionless gate-all-around thin-film transistors and compared the electrical characteristics of single-NS and stacked-NS structures. The performance of the multi-gate and gate-all-around transistors was then further analyzed. The stacked gate-all-around thin-film transistor exhibited superior performance and excellent temperature design flexibility. In brief, the stacked gate-all-around structure for thin-film transistors structure has the potential to overcome the challenges associated with downscaling.INDEX TERMS Gate-all-around (GAA), junctionless (JL), nanosheet (NS), stacked structure, thin-film transistor (TFT).
This work demonstrates the stacked ten nanosheet-type double-channels with multi-gate thin-film transistor (stacked NS). For comparison, this work also fabricated the stacked planar device which top view width is equal to the stacked NS device. The stacked NS device shows superior electrical properties, including high driving current (>10 −6 A um −1 ) and subthreshold slope (199 mV dec −1 ). Moreover, this work also discusses the variable temperature electrical properties and simulates the physical characteristics of the stacked devices. This stacked structure is fabricated through a simple process and has the large potential for the multilayer 3D stacked integrated applications.
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