Impact of Ti/TiN (Glue/Barrier Layer) Formation on Ultra-thin Gate Oxide Reliability (HCI and NBTI) for Deep Sub-micron CMOS Transistors

Liu, Chuan H.; Chen, M.G.; Yang, Yi-Yun; Loh, Y.T.

doi:10.7567/ssdm.2003.p4-14

Extended Abstracts of the 2003 International Conference on Solid State Devices and Materials 2003

DOI: 10.7567/ssdm.2003.p4-14

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Impact of Ti/TiN (Glue/Barrier Layer) Formation on Ultra-thin Gate Oxide Reliability (HCI and NBTI) for Deep Sub-micron CMOS Transistors

Chuan H. Liu¹,

M.G. Chen²,

Yi-Yun Yang³

et al.

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Impact of Ti/TiN (Glue/Barrier Layer) Formation on Ultra-thin Gate Oxide Reliability (HCI and NBTI) for Deep Sub-micron CMOS Transistors

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