In addition to synthesizing biofunctionalized magnetic nanopaticles for the purpose of magnetically labeling biomolecules, a system to measure the ac magnetic susceptibility of the labeled sample was developed. When a targeted biomolecule was mixed with magnetic fluid possessing biofunctionalized magnetic nanoparticles, portions of magnetic nanoparticles agglomerated to form clusters due to the association with the targeted biomolecule. Due to the formation of magnetic clusters, the measured ac magnetic susceptibility reduced. The relationship between the mixed-frequency ac magnetic susceptibility reduction and the amount of the detected biomolecule was established.

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In this work, we report a ferroelectric memory with strained‐gate engineering. The memory window of the high strain case was improved by ∼71% at the same ferroelectric thickness. The orthorhombic phase transition (from ferroelectric to anti‐ferroelectric transition) plays a key role in realizing negative capacitance effect at high gate electric field. Based on a reliable first principles calculation, we clarify that the gate strain accelerates the phase transformation from metastable monoclinic to orthorhombic and thus largely enhances the ferroelectric polarization without increasing dielectric thickness. This ferroelectric strain technology shows the potential for emerging device application.

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In this work, we investigated the negative capacitance behavior of novel ferroelectric versatile memory with low-voltage-driven and fast ferroelectric switching. The combined storage mechanism strengthened the stability of ferroelectric polarization by interface aligned dipoles. The simulation results of first principle calculation indicated that the monoclinic-like orthorhombic phase of ferroelectric hafnium oxide facilitated the occurrence of S-shaped negative capacitance behavior. Furthermore, the control of phase transition may affect ferroelectric property and negative capacitance effect during program and erase states.The ferroelectric memory using CMOS-compatible hafniumoxide-based materials [1][2][3][4][5][6][7][8][9][10] is the potential candidate among emerging memories because of its fast switching speed, long endurance and low voltage operation. Recently, the ferroelectric transistor also has made significant progress due to negative capacitance effect. [11,12] The negative capacitance effect in ferroelectric dielectrics has been proposed, [11][12][13][14][15][16][17] but experimental observation based on ferroelectric characteristics and physical mechanism model is less revealed in ferroelectric transistor memory device. Our previous study reported a versatile ferroelectric memory, [18][19][20] which is a promising candidate for next-generation dynamic random access memory (DRAM) or nonvolatile memory (NVM). To improve the stability of ferroelectric polarization, we choose a top charge-trapped zirconium-silicon oxide (ZrSiO) because of its large band gap to strengthen the spontaneous polarization of hafniumzirconium oxide (HfZrO) during memory switching operation. According to previous study on polarization degradation, the migration of charged oxygen vacancies through electric field is key factor in polarization fatigue, especially for those along the polarization axis. [4][5][6] Thus, oxygen vacancy may impact fast ferroelecrtric switching. To prevent this issue, we adopt a chargetrapping approach forming the interface aligned dipoles between top ZrSiO trapping layer and bottom HfZrO ferroelectric layer to reduce the migration effect of charged oxygen vacancies. [18] After a series of trials, we successfully demonstrated that the memory property of ferroelectric memory can be effectively improved by the combined storage mechanism of charge-trapping and ferroelectric domain. In this work, we further investigated ferroelectric negative capacitance behavior and underlying physical mechanism of ferroelectric versatile memory, which is very important for energyefficient switching of next-generation memory technology.Experiments: The fabrication procedure of memory device is simply described as follows. First, a 3.6-nm SiO 2 grown by dry oxidation process of vertical furnace was used as a bottombuffered oxide. Then the 21-nm-thick HZO ferroelectric layer and 7.5-nm-thick ZSO trapping layer were deposited by a evaporation and a sputter system, respectively. To make a performance comparison, a control ferr...

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