Effects of a lightly-doped-drain (LDD) implantation condition on the device characteristics of poly-Si TFT have been studied. For a LDD implantation dose of 2-4 × 10 13 cm −2 , no significantly large difference in on-state current and off-state leakage is found. For a LDD implantation energy of 50-100 keV, however, the higher LDD implantation energy results in smaller off-state leakage and more reduction of the kink effect. These results are attributable to the more gradual and more widely distributed LDD dopant profile and thus the reduction of electric field near the drain region. As a result, a poly-Si TFT with better device performance and I on /I off ratio can be implemented through the proper scheme of the LDD implantation condition.
A novel polycrystalline silicon (poly-Si) thin film transistor (TFT) formed by using the large-angle-tilt-implanted-drain (LATID) scheme has been proposed. The LATID TFT can achieve much smaller off-state leakage than the lightly doped drain (LDD) TFT. The result is attributable to the reduced electric field near the drain region and thus more effective suppression of carrier emission via trap states. Moreover, the on-state current does not have a large difference in comparison with the LDD TFT, due to the gate-overlapped structure formed by using a simple fabrication process. As a result, a poly-Si TFT with excellent device characteristics and a high on/off current ratio can be implemented by simply using the LATID fabrication scheme.
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