High-performance polycrystalline-Si thin film transistors formed by using large-angle-tilt implanted drains

Abstract

A novel polycrystalline silicon (poly-Si) thin film transistor (TFT) formed by using the large-angle-tilt-implanted-drain (LATID) scheme has been proposed. The LATID TFT can achieve much smaller off-state leakage than the lightly doped drain (LDD) TFT. The result is attributable to the reduced electric field near the drain region and thus more effective suppression of carrier emission via trap states. Moreover, the on-state current does not have a large difference in comparison with the LDD TFT, due to the gate-overlapped structure formed by using a simple fabrication process. As a result, a poly-Si TFT with excellent device characteristics and a high on/off current ratio can be implemented by simply using the LATID fabrication scheme.

Formation of sub-micrometer polycrystalline-SiGe thin-film transistors by using a thinned channel layer

“…This is one of the bias-dependent issues caused by defects in poly-Si TFT devices, which cause poor switching characteristics such as low on/off current ratio [3][4][5][6][7]. It has been reported that various drain structures can decrease the leakage current in poly-Si TFTs due to reduction of electric field intensity near the drain region [8][9][10][11][12][13].…”

High-performance p-channel LTPS-TFT using HfO2gate dielectric and nitrogen ion implantation

“…High-performance low-temperature poly-Si thin-film transistors (LTPS-TFTs) have attracted much attention for the development of active-matrix liquid crystal displays (AMLCDs) on a glass substrate as the pixel-driving device and the integrated circuits to realize system-on-panel (SOP) [1][2][3][4][5]. However, the highest temperature of a TFT manufacturing process for SOP is limited to the melting point of the glass substrate.…”

Formation of thin-film transistors with a polycrystalline hetero-structure channel layer

“…It has been reported that various drain structures can decrease the leakage current in the polysilicon TFTs due to reduction of electric field intensity near the drain region [7][8][9][10][11]. On the other hand, channel engineering has been employed to improve device characteristics including shortchannel effect in ultra-large-scale-integrated circuits.…”