High-performance p-channel LTPS-TFT using HfO₂gate dielectric and nitrogen ion implantation

Abstract

In this communication, a high-performance p-channel low-temperature poly-Si thin-film transistor with HfO 2 gate dielectric and nitrogen ion implantation is demonstrated for the first time. A low threshold voltage V TH = −0.8 V, excellent subthreshold swing S.S. = 0.123 V/decade, high field effect mobility μ FE = 64.14 cm 2 V −1 s −1 and high driving current I Dsat = 9.14 μA μm −1 @ 3 V operation voltage of the p-channel LTPS-TFT can be achieved. The high performance characteristics are attributed to the very low effective oxide thickness EOT = 8.4 nm provided by the HfO 2 gate dielectric and the passivation of effective interface states and grain boundary traps by the nitrogen ion implantation treatment. It would be very suitable for the application of a high-speed and low-power pixel-driving device in flat-panel displays.

High-performance poly-Si TFT with ultra-thin channel film and gate oxide for low-power application

“…As shown in figures 2(a) and (b), the on-state current of the UTB-TFT with a 10 nm gate oxide is much higher than that of the UTB-TFT with a 20 nm gate oxide. Even though the on-state current of the UTB-TFT is much lower than that of the C-TFT, it can be further complemented by a thinner gate oxide or by using a high-κ gate dielectric [9,10,23]. Especially for the traditional poly-Si TFT with a general gate oxide thickness of around 50-100 nm, the gate oxide thickness has great potential to be reduced [24,25].…”

“…With increasing demands for high-level applications, performance requirements for LTPS-TFTs have become critical. Numerous methods have been proposed to realize highperformance poly-Si TFTs, such as employing high-κ gate dielectrics [9,10], plasma treatments [11,12], advanced crystallization processes [13,14], and the implant-to-silicide technique [15]. Nevertheless, while the drive current of LTPS-TFTs can be easily improved, their leakage current is much harder to suppress.…”

High-performance sidewall damascened tri-gate poly-si TFTs with the strain proximity free technique and stress memorization technique

“…In order to continuously keep up with the evolution of Moore's law, 3D ICs are one of the most promising candidates to fulfill the demand of low cost, high density, highperformance, and multi-functional integration on a chip using high-performance poly-Si TFTs. Nowadays, there are many methods that have been proposed to acquire high-performance poly-Si TFTs, including multiple gate configurations [4][5][6][7][8], high-k metal gate-stack [9,10], plasma treatments [11,12], novel crystallization techniques [13,14], and strain techniques [15,16].…”

Investigation of Al-Doped ZnO Channel Layer in ZnO-Based Transparent Thin-Film Transistors

“…At present, the TFTs available on the market are mostly made of amorphous Si (a-Si) films and low-temperature polycrystalline Si (poly-Si) films. 1,2) However, because undesirable photocurrents are induced in the TFTs under light illumination, the working state is interfered with the photocurrents and the display quality is degraded. Recently, wideband-gap semiconductors have been used to fabricate transparent TFTs (TTFTs).…”