This study successfully demonstrates the application of inorganic p-type nickel oxide (NiOx ) as electrode interlayer for the fabrication of NiOx /CH3 NH3 PbI3 perovskite/PCBM PHJ hybrid solar cells with a respectable solar-to-electrical PCE of 7.8%. The better energy level alignment and improved wetting of the NiOx electrode interlayer significantly enhance the overall photovoltaic performance.

PSS-free devices have potential applications in the design of future cost-effective, low-weight, and stable solar cells.

In this study, we developed a high-performance low-temperature polycrystalline silicon thin-film transistor (LTPS-TFT) incorporating an ultra thin Eu 2 O 3 gate dielectric. High-j Eu 2 O 3 LTPS-TFT annealed at 500 C exhibits a low threshold voltage of 0.16 V, a high effective carrier mobility of 44 cm 2 /V-s, a small subthreshold swing of 142 mV/decade, and a high I on /I off current ratio of 1.34 Â 10 7. These significant improvements are attributed to the high gate-capacitance density due to the adequate quality of Eu 2 O 3 gate dielectric with small interfacial layer of effective oxide thickness of 2.5 nm. Furthermore, the degradation mechanism of positive bias temperature instability was studied for a high-k Eu 2 O 3 LTPS-TFT device. V

We have successfully demonstrated SONOS memories with embedded Si-NCs in silicon nitride. This new structure exhibits excellent characteristics in terms of larger memory windows and longer retention time compared to control devices. Using the same thickness 2.5 nm of the bottom tunneling oxide, we found that N 2 O is better than O 2 oxide. Retention property is improved when the thickness of N 2 O is increased to 3.0 nm.

In this communication, a high-performance p-channel low-temperature poly-Si thin-film transistor with HfO 2 gate dielectric and nitrogen ion implantation is demonstrated for the first time. A low threshold voltage V TH = −0.8 V, excellent subthreshold swing S.S. = 0.123 V/decade, high field effect mobility μ FE = 64.14 cm 2 V −1 s −1 and high driving current I Dsat = 9.14 μA μm −1 @ 3 V operation voltage of the p-channel LTPS-TFT can be achieved. The high performance characteristics are attributed to the very low effective oxide thickness EOT = 8.4 nm provided by the HfO 2 gate dielectric and the passivation of effective interface states and grain boundary traps by the nitrogen ion implantation treatment. It would be very suitable for the application of a high-speed and low-power pixel-driving device in flat-panel displays.

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