High-performance sidewall damascened tri-gate poly-si TFTs with the strain proximity free technique and stress memorization technique

Abstract

In this paper, strained channel-sidewall damascened tri-gate polycrystalline silicon thin-film transistors (SC-SWDTG TFTs) have been successfully fabricated and then demonstrated by an innovative process flow. This process flow without the use of advanced lithography processes combines the sidewall damascened technique (SWDT) and two strain techniques, namely, the strain proximity free technique (SPFT), and the stress memorization technique (SMT), in the poly-Si channels. It has some advantages: (1) the channel shapes and dimensions can be effectively controlled by the wet etching processes and the deposition thickness of the tetraethoxysilane (TEOS) oxide; (2) the source/drain (S/D) resistance can be significantly decreased by the formation of the raised S/D structures; (3) the SPFT, SMT, and the rapid thermal annealing (RTA) treatment can enhance the performance of the SC-SWDTG TFTs without the limitation of the highly scaling stress liner thickness in deep-submicron TFTs. Thus, the SC-SWDTG TFTs exhibit a steep subthreshold swing (S.S.)∼110 mV/dec., an extremely small drain induced barrier lowing (DIBL) ∼12.2 mV V −1 , and a high on/off ratio ∼10 7 (V D =1 V) without plasma treatments for future three-dimensional integrated circuits (3D ICs) applications.

Formation and characterization of high-performance silicon thin-film transistors with and without location-controlled grain boundary

“…The development of low-temperature polycrystalline-silicon (LTPS) thin-film transistors (TFTs) has been proceeded for a wide variety of applications in high-tech industry, such as flat-panel displays (FPDs) and 3D integrated circuits (3D ICs) [1][2][3][4][5]. A number of LTPS technologies, which can be classified as furnace annealing-based methods and laser crystallization methods, have been proposed to produce Si layers for the active layer of LTPS TFTs [6][7][8][9][10][11][12][13][14][15]. However, a long-time annealing process (typically for hours) and a poor quality of the crystallized Si layer are drawbacks of the furnace annealing-based method, such as solid-phase crystallization and metal-induced lateral crystallization.…”