Phase-change random-access memory (PCRAM) is one of the leading candidates for next-generation data-storage devices, but the trade-off between crystallization (writing) speed and amorphous-phase stability (data retention) presents a key challenge. We control the crystallization kinetics of a phase-change material by applying a constant low voltage via prestructural ordering (incubation) effects. A crystallization speed of 500 picoseconds was achieved, as well as high-speed reversible switching using 500-picosecond pulses. Ab initio molecular dynamics simulations reveal the phase-change kinetics in PCRAM devices and the structural origin of the incubation-assisted increase in crystallization speed. This paves the way for achieving a broadly applicable memory device, capable of nonvolatile operations beyond gigahertz data-transfer rates.

Although organic semiconductors have received the most attention, the development of compatible passive elements, such as interconnects and electrodes, is also central to plastic electronics. For this, ligand-protected metal-cluster films have been shown to anneal at low temperatures below 250 degrees C to highly conductive metal films, but they suffer from cracking and inadequate substrate adhesion. Here, we report printable metal-cluster-polymer nanocomposites that anneal to a controlled-percolation nanostructure without complete sintering of the metal clusters. This overcomes the previous challenges while still retaining the desired low transformation temperatures. Highly water- and alcohol-soluble gold clusters (75 mg ml-1) were synthesized and homogeneously dispersed into poly(3,4-ethylenedioxythiophene) to give a material with annealed d.c. conductivity tuneable between 10(-4) and 10(5) S cm-1. These composites can inject holes efficiently into all-printed polymer organic transistors. The insulator-metal transformation can also be electrically induced at 1 MV cm-1, suggesting possible memory applications.

We report the characterization of strain components in transistor structures with silicon–germanium (Si0.75Ge0.25) and silicon–carbon (Si0.99C0.01) stressors grown by selective epitaxy in the source and drain regions. The spacing between the source and drain stressors is 35nm. Lattice strain analysis was performed using high-resolution transmission electron microscopy (HRTEM) and diffractograms obtained by fast Fourier transform of HRTEM images. The lateral strain component εxx and the vertical strain component εzz were derived from the (220) and (002) reflections in the diffractogram, respectively. SiGe source and drain stressors lead to lateral compressive strain and vertical tensile strain in the Si channel. On the other hand, the SiC source and drain stressors give rise to lateral tensile strain and vertical compressive strain in the Si channel, an effect complementary to that of SiGe source∕drain stressors. The results of this work will be useful for channel strain engineering in complementary metal-oxide-semiconductor transistors.

The device physics and electrical characteristics of the germanium (Ge) tunneling field-effect transistor (TFET) are investigated for high performance and low power logic applications using two dimensional device simulation. Due to the high band-to-band tunneling rate of Ge as compared to Si, the Ge TFET suffers from excessive off-state leakage current Ioff despite its higher on-state current Ion. It is shown for the first time that the high off-state leakage due to the drain-side tunneling in the Ge TFET can be effectively suppressed by controlling the drain doping concentration. A lower drain doping concentration reduces the electric field and increases the tunneling barrier width in the drain side, giving a significantly reduced off-state leakage. To increase Ion with a steeper subthreshold swing S, source doping concentration is increased to reduce the bandgap and narrow the tunneling width. Device design and physics detailing the impact of drain and source engineering on the performance of Ge TFET are discussed.

In this letter, we developed an improved ultrafast measurement method for threshold voltage th measurement of MOSFETs. We demonstrate -curve measurement within 1 s to extract the threshold voltage of MOSFET. Errors arising from MOSFET parasitics and measurement setup are analyzed quantatatively. The ultrafast th measurement is highly needed in the investigation of gate dielectric charge trapping effect when traps with short detrapping time constants are present. Application in charge trapping measurement on HfO 2 gate dielectric is demonstrated.