In this paper, a CMOS image sensor using floating capacitor load readout operation has been discussed. The floating capacitor load readout operation is used during pixel signals readout. And this operation has two features: 1. in-pixel driver transistor drives load capacitor without current sources, 2. parasitic capacitor of pixel output vertical signal line is used as a sample/hold capacitor. This operation produces three advantages: a smaller chip size, a lower power consumption, and a lower output noise than conventional CMOS image sensors. The prototype CMOS image sensor has been produced using 0.18 m 1-Poly 3-Metal CMOS process technology with pinned photodiodes. The chip size is 2.5 mm H 2.5 mm V , the pixel size is 4.5 m H 4.5 m V , and the number of pixels is 400 H 300 V . This image sensor consists of only a pixel array, vertical and horizontal shift registers, column source followers of which height is as low as that of some pixels and output buffers. The size of peripheral circuit is reduced by 90.2 % of a conventional CMOS image sensor. The power consumption in pixel array is reduced by 96.9 %. Even if the power consumption of column source follower is included, it reduced by 39.0 %. With an introduction of buried channel transistors as in-pixel driver transistors, the dark random noise of pixels of the floating capacitor load readout operation CMOS image sensor is 168 V rms . The noise of conventional image sensor is 466 V rms ; therefore, reduction of 63.8 % of noise was achieved.
This paper presents a CMOS image sensor using column-parallel forward noise-canceling circuitry (FNC) for noise reduction of the pixel readout chain. A proposed FNC has been developed to provide a sharp noise-filtering in order to suppress both random noise and temporal line noise. The readout architecture consists of a high-gain amplifier with correlated-doublesampling, a FNC, and sample-and-hold circuits. A prototype 400 H 250 V CMOS image sensor has been fabricated in a 0.18 m 1-Poly 3-Metal CMOS technology with pinned-photodiodes. The measured input-referred noise of the signal readout chain is 65 V rms , which has been reduced by 24 % compared to that of the conventional readout architecture.
In this paper, a new column-parallel analog readout architecture, which is composed of a high-gain amplifier, a forward noise-canceling circuitry (FNC), and sample-and-hold (S/H) capacitors, has been presented for low-noise CMOS image sensors (CIS). A FNC has been proposed to provide a sharp noise-filtering for high-frequency noise arising from the readout signal chain, which effectively reduces random noise of the pixel source follower and column amplifier. In order to keep the high-sensitivity and high-dynamic range output, dual-gain readout chains have been adopted. A prototype 400H × 250V CIS using the readout architecture with the FNC was fabricated in a 0.18 µm 1-poly 3-metal CMOS process with pinned-photodiodes. The experimental results revealed the input-referred noise of the proposed readout architecture was 65 µVrms, which has been reduced by 24% compared to that of the conventional readout architecture.
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