A Column-Parallel Hybrid ADC using SAR and Single-Slope with Error Correc-tion for CMOS Image Sensors

Li, T. L.; Sakai, Shin-ichi; Kawada, Shun; Goda, Yasuyuki; Wakashima, Shunichi; Kuroda, Rihito; Sugawa, Shigetoshi

doi:10.7567/ssdm.2012.j-1-4

Cited by 1 publication

(1 citation statement)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This paper presents a column-parallel two-step ADC using SAR and SS hybrid architectures to achieve both fast conversion and low power consumption without using a high frequency clock and a large capacitor DAC. 27) In addition, an error correction methodology for nonlinearity reduction is proposed to calibrate the capacitance mismatches in the capacitor DAC arising from the fabrication process of the capacitor-array. An 11-bit hybrid ADC has been implemented as a prototype design.…”

Section: Introductionmentioning

confidence: 99%

A Column-Parallel Hybrid Analog-to-Digital Converter Using Successive-Approximation-Register and Single-Slope Architectures with Error Correction for Complementary Metal Oxide Silicon Image Sensors

Sakai

Kawada

et al. 2013

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

In this paper, a column-parallel hybrid analog-to-digital converter (ADC) architecture taking the advantages of both successive-approximation-register (SAR) and single-slope (SS) architectures has been developed for CMOS image sensors. The proposed architecture achieves high conversion speed and low power consumption without requiring a high clock frequency and a large number of capacitors. Moreover, an error correction methodology has been presented to calibrate capacitance mismatches in a SAR capacitor array for linearity improvement. An 11-bit hybrid prototype ADC has been implemented in a 0.18-µm 1-poly 5-metal standard CMOS process. The conversion time is 1.225 µs with a maximum operation clock frequency of 40 MHz and it consumes 48 µW. With the proposed error correction, the measured differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.40/-0.44 least significant bit (LSB) and +1.21/-1.12 LSB, respectively.

show abstract

Section: Introductionmentioning

confidence: 99%