In June 2007, Intel announced a new pixelated mask technology. This technology was created to address the problem caused by the growing gap between the lithography wavelength and the feature sizes patterned with it. As this gap has increased, the quality of the image has deteriorated. About a decade ago, Optical Proximity Correction (OPC) was introduced to bridge this gap, but as this gap continued to increase, one could not rely on the same basic set of techniques to maintain image quality. The computational lithography group at Intel sought to alleviate this problem by experimenting with additional degrees of freedom within the mask. This paper describes the resulting pixelated mask technology, and some of the computational methods used to create it. The first key element of this technology is a thick mask model. We realized very early in the development that, unlike traditional OPC methods, the pixelated mask would require a very accurate thick mask model. Whereas in the traditional methods, one can use the relatively coarse approximations such as the boundary layer method, use of such techniques resulted not just in incorrect sizing of parts of the pattern, but in whole features missing. We built on top of previously published domain decomposition methods, and incorporated limitations of the mask manufacturing process, to create an accurate thick mask model. Several additional computational techniques were invoked to substantially increase the speed of this method to a point that it was feasible for full chip tapeout. A second key element of the computational scheme was the comprehension of mask manufacturability, including the vital issue of the number of colors in the mask. While it is obvious that use of three or more colors will give the best image, one has to be practical about projecting mask manufacturing capabilities for such a complex mask. To circumvent this serious issue, we eventually settled on a two color mask -comprising plain glass and etched glass. In addition, there were several smaller manufacturability concerns, for example a "1X1" glass pillar (an isolated 0 phase pixel) were susceptible to collapse under the stress of mask processing, and therefore these had to be constrained out of the final configuration. A third key element was defining the objective function. We experimented with a large number of choices and eventually settled on a form that allows us to trade-off fidelity and contrast. A fourth key element was the optimization algorithm. The number of possible configurations for a trillion pixels present on our final product mask is greater than the number of total elementary particles in the known universe, so finding the proverbial needle in this haystack was difficult to say the least. We chose a mixture of stochastic and direct descent algorithms to find an arrangement that meets the demands. While we have not proved we are close to the absolute global minimum, we conducted several experiments to suggest this is the case. A fifth key element, and a large one at that, was scalin...

Novel RET-Pixelated Phase Mask (PPM) is proposed as a novel Resolution Enhancement Technique (RET). PPM is made of pixels of various phases with lateral dimensions significantly smaller than the illuminating radiation wavelength. Such PPM with a singular choice of pixel dimensions acts as a mask with variable phase and transmission due to radiation scattering and attenuation on pixel features with the effective intensity and phase modulated by the pixel layout. Key properties of the pixelated phase masks, the steps for their practical realization, and the benefits to random logic products discussed. Wafer patterning performance and comparative functional yield results obtained for a 65nm node microprocessor patterned with PPM, as well as current PPM limitations are also presented.

Area density scaling in integrated circuits, defined as transistor count per unit area, has followed the famous observation-cum-prediction by Gordon Moore for many generations. Known as "Moore's Law" which predicts density doubling every 18-24 month, it has provided all important synchronizing guidance and reference for tools and materials suppliers, IC manufacturers and their customers as to what minimal requirements their products and services need to meet to satisfy technical and financial expectations in support of the infrastructure required for the development and manufacturing of corresponding technology generation nodes. Multiple lithography solutions are usually under considerations for any given node. In general, three broad classes of solutions are considered: evolutionary -technology that is extension of existing technology infrastructure at similar or slightly higher cost and risk to schedule; revolutionary -technology that discards significant parts of the existing infrastructure at similar cost, higher risk to schedule but promises higher capability as compared to the evolutionary approach; and last but not least, disruptiveapproach that as a rule promises similar or better capabilities, much lower cost and wholly unpredictable risk to schedule and products yields. This paper examines various lithography approaches, their respective merits against criteria of respective infrastructure availability, affordability and risk to IC manufacturer's schedules and strategy involved in developing and selecting best solution in an attempt to sort out key factors that will impact the decision on the lithography choice for large-scale manufacturing for the future technology nodes.

Multiple paths exists to provide lithography solutions pursuant to Moore's Law for next 3-5 generations of technology, yet each of those paths inevitably leads to solutions eventually requiring patterning at k 1 < 0.30 and below. In this article, we explore double exposure single development lithography for k 1 ≥ 0.25 (using conventional resist) and k 1 < 0.25 (using new out-of-sight out-of-mind materials). For the case of k 1 ≥ 0.25, we propose a novel double exposure inverse lithography technique (ILT) to split the pattern. Our algorithm is based on our earlier proposed single exposure ILT framework, and works by decomposing the aerial image (instead of the target pattern) into two parts. It also resolves the phase conflicts automatically as part of the decomposition, and the combined aerial image obtained using the estimated masks has a superior contrast.For the case of k 1 < 0.25, we focus on analyzing the use of various dual patterning techniques enabled by the use of hypothetic materials with properties that allow for the violation of the linear superposition of intensities from the two exposures. We investigate the possible use of two materials: contrast enhancement layer (CEL) and two-photon absorption resists. We propose a mathematical model for CEL, define its characteristic properties, and derive fundamental bounds on the improvement in image log-slope. Simulation results demonstrate that double exposure single development lithography using CEL enables printing 80nm gratings using dry lithography. We also combine ILT, CEL, and DEL to synthesize 2-D patterns with k 1 = 0.185. Finally, we discuss the viability of two-photon absorption resists for double exposure lithography.

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