Marching to the beat of Moore's Law

Abstract

Area density scaling in integrated circuits, defined as transistor count per unit area, has followed the famous observation-cum-prediction by Gordon Moore for many generations. Known as "Moore's Law" which predicts density doubling every 18-24 month, it has provided all important synchronizing guidance and reference for tools and materials suppliers, IC manufacturers and their customers as to what minimal requirements their products and services need to meet to satisfy technical and financial expectations in support of the infrastructure required for the development and manufacturing of corresponding technology generation nodes. Multiple lithography solutions are usually under considerations for any given node. In general, three broad classes of solutions are considered: evolutionary -technology that is extension of existing technology infrastructure at similar or slightly higher cost and risk to schedule; revolutionary -technology that discards significant parts of the existing infrastructure at similar cost, higher risk to schedule but promises higher capability as compared to the evolutionary approach; and last but not least, disruptiveapproach that as a rule promises similar or better capabilities, much lower cost and wholly unpredictable risk to schedule and products yields. This paper examines various lithography approaches, their respective merits against criteria of respective infrastructure availability, affordability and risk to IC manufacturer's schedules and strategy involved in developing and selecting best solution in an attempt to sort out key factors that will impact the decision on the lithography choice for large-scale manufacturing for the future technology nodes.

Contact layer decomposition to enable DSA with multi-patterning technique for standard cell based layout

“…As multiple patterning lithography (MPL) remains the top next-generation lithography candidate with 193 nm immersion (193i) lithography, mitigating the cost incurred by multiple patterning becomes a critical issue [1]. Also, as the EUV technique has been continually delayed, when it really comes out, it will be most likely to adopt double patterning technique to handle the challenges in 7 nm technology node.…”

Intel design for manufacturing and evolution of design rules

“…1,2,3 Design rules have to change and DFM methodology has to continue to improve to enable Moore's law scaling. This paper will discuss our approach to DFM though co-optimization across design and process.…”

Compensation of overlay errors due to mask bending and non-flatness for EUV masks

“…The non-flatness specification for EUV substrates is <40 nm by 2013 [1], which corresponds to around the time that EUV is expected to be in high volume manufacturing (HVM) [2]. 30 nm PV non-flatness is extremely difficult to achieve on EUV substrates simultaneously with low defectivity.…”