San #24 Nongseo-Lee, Kihung-Eup, Y ongin-G un, Kyungki-Do, Korea Introduction As the storage electrode area is decreasing with increase of DRAM density, the various stack structures have been extensively developed by a number of researchers. The Fin (1,2), the Spread Stack (3), and the Cylinder families (4,5) are proposed as the possible stack structures for high density DRAM . Recently, HSG (Hemi Spherical Grain ) or Rugged Surface technique (6,7,8) are reported for surface area enhancement.However, the capacitance of those stack structures can hardly satisfy the capacitance requirement for 256Mb DRAM within the limited design rule.This paper introduces MVP ( Micro Yillus Eatterning ) technology which delivers the maximized cell capacitance. With simple process integration, the MVP technology will be a strong candidate for the future stack cell capacitor process.
A poly-Si/Al,O,/poly-Si capacitor is developed for the simple integration of 256Mb DRAM and beyond.The oxide equivalent thickness (Tow) of AI,O, capacitor was achieved as small as 2 8 m , which is about 1.7 times smaller than that of advanced NO capacitor. Especially, the pre-treatment before the deposition of A1,03 f i l m plays crucial role for stable device performance. Moreover, one of the distinguished characteristics of A1,0, capacitor is that the capacitance was even enhanced by performing the conventional DRAM processes, including high temperature planarization known as BPSG flow, without degrading the leakage characteristics.suffer fiom the lack of the required capacitance even with the stacked storage node with rugged surface. The storage capacitor integration with TqO, and BST requires the major modification of the electrode materials, which produces many difficulties during the full integration. Therefore, it is highly desirable to develop new capacitors with conventional poly-Si as both storage and plate electrodes, which provide sufficient capacitance in a limited area. In this paper, the excellent physical and dielectric properties of Al,O, film as well as its applicability to conventional 256Mb DRAM and beyond are presented.[ 11 Capacitor Fabrication IntroductionFor the 0.21 pm DRAMS and beyond, the conventional storage capacitors, consisting of Nitride/Oxide (NO) dielectrics and poly-Si electrodes, As shown in Fig. 1 (a), the simple stacked Al,O, capacitors with 1 .Opm-height storage node were integrated into a 256Mb DRAM with a feature size of 0.2 1 pm. Fig. 1. (a) A vertical view of the simple stacked A1,0, capacitors integrated into a 256 Mb DRAM with a feature size of 0.26pm. (b) TEM micrograph of A1,0, storage capacitor.
We propose an advanced DRAM cell structure with a capacitor formed after patterning the first-level metal. Since the second-level-metal which will be patterned after forming storage capacitors usually have relaxed design rule, a sufficient cell capacitance can be obtained in this structure by simply increasing the stack height of the capacitor. A limited thermal cycle after the storage node formation makes it possible to use Ta2O5 as a dielectric material without causing high temperature related leakage problems.
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