A 0.13 μm DRAM technology for giga bit density stand-alone and embedded DRAMs

Kim, K.N.; Chung, Taeyoung; Jeong, Hae-Yong; Moon, Joo-Tae; Park, Y.W.; Jeong, Gitae; Lee, K.H.; Koh, G.H.; Shin, Dong-won; Hwang, Young‐Ha; Kwak, Dong-Hwa; Uh, Hyung Soo; Ha, Daewon; Lee, J.W.; Shin, Susanna; Lee, M.H.; Chun, Yeoun Sook; Lee, J.K.; Park, B.J.; Oh, Jeong-Hoon; Lee, J.G.; Lee, S.H.

doi:10.1109/vlsit.2000.852748

Cited by 7 publications

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“…To improve the performance of memory cell, many technologies have been proposed and characterized recently [1,2]. Especially, low voltage and high performance DRAM for the various applications, such as graphic, mobile, and network, requires the reduction of parasitic resistance and capacitance.…”

Section: Introductionmentioning

confidence: 99%

Recessed junction and low energy n-junction implantation characteristics

Lee¹,

Yoo²,

Lee³

et al. 2002

Ion Implantation Technology. 2002. Proceedings of the 14th International Conference On

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The characteristics of cell transistor with low energy junction implantation and recessed junction, which is formed by in_situ phosphorus doped selective silicon growth, are investigated. Adding the low energy n-junction implantation drastically reduces the contact resistance of pad/n-junction. And also, the drive current is improved without any degradation of BV (Breakdown Voltage) and leakage characteristics. Plasma damage free TDSE (Thermal Desorption of Silicon Etching) processing using the Cl 2 gas chemistry in UHV CVD Chamber is used to controll the junction depth. The recessed junction is formed with phosphorusdoped silicon using the SEG (Selective Epitaxial Growth) process and the characteristics of recessed junction are evaluated.

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Section: Introductionmentioning

confidence: 99%