Micro villus patterning (MVP) technology for 256 Mb DRAM stack cell

Abstract

San #24 Nongseo-Lee, Kihung-Eup, Y ongin-G un, Kyungki-Do, Korea Introduction As the storage electrode area is decreasing with increase of DRAM density, the various stack structures have been extensively developed by a number of researchers. The Fin (1,2), the Spread Stack (3), and the Cylinder families (4,5) are proposed as the possible stack structures for high density DRAM . Recently, HSG (Hemi Spherical Grain ) or Rugged Surface technique (6,7,8) are reported for surface area enhancement.However, the capacitance of those stack structures can hardly satisfy the capacitance requirement for 256Mb DRAM within the limited design rule.This paper introduces MVP ( Micro Yillus Eatterning ) technology which delivers the maximized cell capacitance. With simple process integration, the MVP technology will be a strong candidate for the future stack cell capacitor process.

The DRAM Array

“…Figures 2.13 and 2.14 present a process cross section of the third type of mbit used in the construction of DRAMs. Using trench storage capacitors, this cell is accordingly called a trench cell [12] [13]. Trench capacitors are formed in the silicon substrate, rather than above the substrate, after etching deep holes into the wafer.…”