No abstract

No abstract

We have developed low temperature, low defect, and low cost SiGe selective epitaxial growth (L 3 SiGe SEG) process using a high throughput batch type CVD process at first time. Defect is eliminated by low temperature pre-cleaning and recess shape control. As a result, we have achieved the high quality SiGe SEG, improving the compressive channel stress and reducing the junction leakage. We also improved the NMOS short channel effects by low temperature SiGe SEG. Finally, in combination of low temperature SiGe SEG, dual stress SiN liner, and low thermal budget metallization, drive current of 725 �A/�m in PMOS and 940 �A/�m in NMOS were achieved at off current (I off ) = 100 nA/�m at drain bias (V DD ) = 1.0 V. Introduction Selective epitaxial growth (SEG) of SiGe in a recessed source/drain (S/D) has been considered to be a promising stressor for enhancing the drive current [1]. Epitaxial SiGe S/D gives a compressive channel stress and increases the hole mobility due to the lattice mismatch between SiGe and Si substrate. We have already reported that the defects in SiGe degrade the short channel effects and the hole mobility due to the enhanced B diffusion and the strain relaxation, respectively [2]. Since SiGe/Si hetero structures are metastable with respect to equilibrium, strain tends to relax at higher SiGe growth temperature ( Fig.1) [3]. Moreover, thermal budget of SiGe epitaxial growth has an impact on the short channel effects of NMOS because of dopants re-distribution ( Fig.1). On the other hand, quality of epitaxial SiGe is generally poor at lower growth temperature, generating defects such as pits near side wall spacer as shown in Fig. 2. These pits formations are mainly due to the plasma damage during recess etching and the insufficient removal of interfacial impurities such as O and C. Poor productivity is also one of limits of low temperature process. In this paper, we propose the low temperature, high quality, and high throughput SiGe SEG process and report impacts of SiGe growth temperature on device performance. Device Process Concept A. Newly Proposed Low Temperature EPIConventional SiGe SEG is normally done by single wafer type low-pressure chemical vapor deposition (LPCVD) system at 650-750 o C with dichlorosilane (DCS) � germane (GeH 4 ) -H 2 mixture gases as a SiGe source. As a Si source gas, DCS is suitable for selective growth but not for low temperature growth because growth rate is extremely low as shown in Fig.3. By using silane (SiH 4 ) gas and further optimization, growth rate is enhanced 10 times at 550 o C in compare with DCS case. With increasing HCl partial pressure in this optimized gas mixture, selective growth is achieved even at low temperature of 550 o C, but growth rate is decreased as shown in Fig.4. However poor productivity of low temperature process could be overcome by adopting a new batch type CVD process. Fig.5 shows our newly proposed low temperature batch type CVD sequence. That maximum temperature is below 600 o C. For example, at the SEG temperature of 550 o C, throu...