High performance 30 nm gate bulk CMOS for 45 nm node with &amp;#x03C3;-shaped SiGe-SD

Ohta, Hiromichi; Kim, Y.; Shimamune, Y.; Sakuma, T.; Hatada, A.; Katakami, A.; Soeda, Takeshi; Kawamura, K.; Kokura, H.; Morioka, Hiroshi; Watanabe, Takashi; Hayami, J.O.Y.; Ogura, J.; Tajima, M.; Mori, Toshihiko; Tamura, N.; Kojima, M.; Hashimoto, Kenji

doi:10.1109/iedm.2005.1609316

Cited by 30 publications

(25 citation statements)

References 7 publications

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“…However, Fig. 1 shows that the increasing device-engineering level modeled by Eta0 parameter is not sufficient to mitigate the DIBL increase with technology scaling, leading to η values higher than 150 mV/V as in [9]. This is due to the relatively slow scaling of T ox and X dep and thus l t as compared to L ef f .…”

Section: Subthreshold Drain Currentmentioning

confidence: 78%

Impact of Technology Scaling on Digital Subthreshold Circuits

Bol

Ambroise

Flandre

et al. 2008

2008 IEEE Computer Society Annual Symposium on VLSI

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Subthreshold circuits exhibit ultra-low energy per operation at the expense of increased delay. In this contribution, the impact of technology scaling on digital subthreshold circuits is investigated. Migrating from 0.25-µm to 32-nm node is shown to considerably lower the energy consumption of a subthreshold 8×8-bit RCA multiplier. When reaching the smallest nodes, limitations come from slow scaling of the static energy consumption and the deteriorating static noise margin, which raises robustness issues when considering process variability. These effects result in a loss of energy efficiency. The use of non-minimum channel length is proposed to improve energy efficiency. At 32-nm node, it reduces total energy consumption by a factor 5.

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Section: Subthreshold Drain Currentmentioning

confidence: 78%

Impact of Technology Scaling on Digital Subthreshold Circuits

Bol

Ambroise

Flandre

et al. 2008

2008 IEEE Computer Society Annual Symposium on VLSI

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“…The effectiveness of strain transfer can be improved by placing eSiGe closer to the pMOS channel, as evidenced by a 1.4× channel strain increase when eSiGe proximity to the channel is reduced from 25 nm to 5 nm for a 45-nm pMOS [17]. eSiGe recess profile also emerged as an effective knob that can be optimized to further enhance strain benefit, which includes the eSiGe recess depth and the "Σ-shaped" eSiGe [18,19]. In addition, process optimization of pre-clean before eSiGe growth, the epitaxial process, and fill levels relative to the channel Si surface (such as flush-fill, under-fill, or over-fill) are all critical to maximize the eSiGe stress benefit.…”

Section: Embedded Sige (Esige)mentioning

confidence: 99%

Advanced strain engineering for state-of-the-art nanoscale CMOS technology

Yang

Cai

2011

Sci. China Inf. Sci.

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The introduction and advancement of strain engineering has been one of the most critical features for the state-of-the-art nanoscale CMOS transistors. This paper provides an overview of the major strain engineering techniques that have remarkably re-shaped the advanced CMOS transistor architecture, including embedded SiGe (eSiGe), embedded Si:C (eSi:C), stress memorization technique (SMT), dual stress liners (DSL), and stress proximity technique (SPT). The advent of high-K/metal-gate (HKMG) also brings in additional strain benefit with its metal gate stressor (MGS) and replacement gate (RMG) process. Strain engineering continues to evolve and will remain to be one of the key performance enablers for the future generation of CMOS technologies. CitationYang B, Cai M. Advanced strain engineering for state-of-the-art nanoscale CMOS technology. Sci China Inf Sci, 2011, 54: 946-958,

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“…Further strain could be induced when the shape of recessed S/D changed from a round shape to sigma (Σ) shape where the SiGe layers locate deeper in the channel region as shown in Figure 5 [41][42][43].…”

Section: Stress Engineeringmentioning

confidence: 99%

The Challenges of Advanced CMOS Process from 2D to 3D

Radamson

Zhang

et al. 2017

Applied Sciences

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Abstract:The architecture, size and density of metal oxide field effect transistors (MOSFETs) as unit bricks in integrated circuits (ICs) have constantly changed during the past five decades. The driving force for such scientific and technological development is to reduce the production price, power consumption and faster carrier transport in the transistor channel. Therefore, many challenges and difficulties have been merged in the processing of transistors which have to be dealed and solved. This article highlights the transition from 2D planar MOSFETs to 3D fin field effective transistors (FinFETs) and then presents how the process flow faces different technological challenges. The discussions contain nano-scaled patterning and process issues related to gate and (source/drain) S/D formation as well as integration of III-V materials for high carrier mobility in channel for future FinFETs.

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High performance 30 nm gate bulk CMOS for 45 nm node with σ-shaped SiGe-SD

Cited by 30 publications

References 7 publications

Impact of Technology Scaling on Digital Subthreshold Circuits

Impact of Technology Scaling on Digital Subthreshold Circuits

Advanced strain engineering for state-of-the-art nanoscale CMOS technology

The Challenges of Advanced CMOS Process from 2D to 3D

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