Technology booster using strain-enhancing laminated SiN (SELS) for 65nm node HP MPUs

Goto, Ken; Satoh, Shuichi; Ohta, Hiromichi; Fukuta, S.; Yamamoto, Takuji; Mori, Toshihiko; Tagawa, Y.; Sakuma, T.; Saiki, Takashi; Shimamune, Y.; Katakami, A.; Hatada, A.; Morioka, Hiroshi; Hayami, Y.; Inagaki, Satoshi; Kawamura, K.; Kim, Y.; Kokura, H.; Tamura, N.; Horiguchi, N.; Kojima, M.; Sugii, T.; Hashimoto, Kouichi

doi:10.1109/iedm.2004.1419111

Cited by 33 publications

(21 citation statements)

References 5 publications

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“…The stress in n-MOSFETs does not increase the v inj as in the p-MOS devices, consequently the stress-induced I ON improvements are larger in p-MOS transistors than in n-MOS ones [78]. [54,56,57,[92][93][94][95][96][97][98][99] Quite interestingly, the simulation prediction of a stressinduced improvement of the I ON disadvantage of pMOSFETs is supported by the experimental data. In fact Fig.…”

Section: Simulation Results For Nano-scale Mosfetsmentioning

confidence: 81%

Semi-classical transport modelling of CMOS transistors with arbitrary crystal orientations and strain engineering

et al. 2009

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This paper reviews the basic methodologies and models used in the semi-classical modelling of CMOS transistors in the framework of the nowadays generalized scaling scenario. The capabilities to describe devices with arbitrary crystal orientations and strain configurations are discussed. Several simulation results are illustrated and compared to the experiments to assess the understanding of the underlying physics and the predictive capabilities of the models. A case study concerning the drain currents in nano-scale uniaxially strained MOSFETs is presented and it shows how the strain engineering may change the traditional on-current disadvantage of the p-MOS compared to the n-MOS transistors.

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Section: Simulation Results For Nano-scale Mosfetsmentioning

confidence: 81%

Semi-classical transport modelling of CMOS transistors with arbitrary crystal orientations and strain engineering

et al. 2009

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“…The benefit of DSL can be further enhanced by increasing the stress film thickness, reducing polysilicon gate height, or reducing sidewall spacer thickness [33]. Novel techniques such as laminated SiN by multilayer deposition or exposure of SiN films to ultraviolet radiation are also shown to enhance the stress of the film [34,35]. Although SiN is commonly used for stress liners, it is also demonstrated that a diamond-like carbon film can be used to achieve an intrinsic compressive stress (> 6 GPa), which is the highest liner in stress applied to MOS transistors so far [36].…”

Section: Dual Stress Liners (Dsl)mentioning

confidence: 97%

Advanced strain engineering for state-of-the-art nanoscale CMOS technology

Yang

Cai

2011

Sci. China Inf. Sci.

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The introduction and advancement of strain engineering has been one of the most critical features for the state-of-the-art nanoscale CMOS transistors. This paper provides an overview of the major strain engineering techniques that have remarkably re-shaped the advanced CMOS transistor architecture, including embedded SiGe (eSiGe), embedded Si:C (eSi:C), stress memorization technique (SMT), dual stress liners (DSL), and stress proximity technique (SPT). The advent of high-K/metal-gate (HKMG) also brings in additional strain benefit with its metal gate stressor (MGS) and replacement gate (RMG) process. Strain engineering continues to evolve and will remain to be one of the key performance enablers for the future generation of CMOS technologies. CitationYang B, Cai M. Advanced strain engineering for state-of-the-art nanoscale CMOS technology. Sci China Inf Sci, 2011, 54: 946-958,

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“…However, for deep submicron VLSI process, the compressive stress caused by shallow trench isolation (STI) would also affect devices mobility; and the STI induced compressive stress can be modified by changing the length from gate to STI edge (LOD) and gate width. Using the HS CESL to enhance device mobility has been proposed popularly and recently [2][3][4][5][6][7][8][9][10][11][12][13], but few studies studied on the interactive stress effect between the thickness of HS CESL, LOD, gate width on device characteristic and hot-carrier reliability especially for silicon-on-insulator (SOI) devices. An appropriate tensile stress will enhance device performance efficiently and avoid excess damages happen.…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, a simple way that enhances devices mobility without accompanying the increase of process steps was required strongly. One of such attempts is modifying the thickness of high-tensile-stress contact etch stop layer (HS CESL) [2][3][4][5][6][7][8][9], length of diffusion (LOD) and gate width [10][11][12][13] to control the tensile and compressive stresses in channel region to improve the channel mobility.…”

Section: Introductionmentioning

confidence: 99%

The impacts of high tensile stress CESL and geometry design on device performance and reliability for 90nm SOI nMOSFETs

Lai

Fang

Lin

et al. 2007

Microelectronics Reliability

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Technology booster using strain-enhancing laminated SiN (SELS) for 65nm node HP MPUs

Cited by 33 publications

References 5 publications

Semi-classical transport modelling of CMOS transistors with arbitrary crystal orientations and strain engineering

Semi-classical transport modelling of CMOS transistors with arbitrary crystal orientations and strain engineering

Advanced strain engineering for state-of-the-art nanoscale CMOS technology

The impacts of high tensile stress CESL and geometry design on device performance and reliability for 90nm SOI nMOSFETs

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