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A highly manufacturable high density embedded SRAM technology with 0.8um2 cell for 90nm technology node has been developed. Based on cell layout study by lithography simulation, both cell layout and key process were carefully optimized and scaled down from those of lOOnm technology. Fabricated SRAM used 0.25um well isolation and O.lum contact showed good functionality down to VDP0.6V. Electrical fuse utilizing MOSFET was also developed for redundancy to avoid Cu/Low-k BEOL damage from laser blow.

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This paper demonstrates a 100 nm generation SOC technology [CMOS IV] for the first time. Three types of core devices are presented with optimized gate oxynitrides for their stand-by power conditions. This advanced LOGIC process is compatible with 0.18 pm2 trench capacitor DRAM and 1.25 pm2 6 Tr. SRAM. Two kinds of high Vdd devices can be prepared by triple gate oxide process. Moreover, for mixed signal applications, Ta2O5 MIM capacitors are introduced into Cu and low-k interconnects. Device Concept Stand-by Power ManagementWhen total solutions for SOC are considered, an increase in the stand-by power caused by leakage currents is one of the major issues, leading to problems with packaging and testing of LSI chips. In addition, as the gate oxide thickness is simply scaled down to < 2 nm driven by Moore's law, the gate direct tunneling current emerges as a device design issue. In this regime, the stand-by power of LSIs becomes limited by the gate current (Ig) as well as by the drain current at off state (I,,s). It is essential to control Ig for a variety of system applications.In Fig. 1, the solid line shows the gate current density in thermal Si02, while the dashed line shows that of oxynitride. By optimizing nitrogen concentration in the gate oxynitride, Ig can be reduced by a factor of I O compared to Si02 so that thinner equivalent oxide thickness can be utilized in addition to the effect of controlling boron penetration [I]. In this graph, the acceptable Ig lines from system demands are also shown for high performance device (HP), standard device (SD) and low leakage device (LL). These three device parameters are summarized in Table 1. HP device achieves high performance and low active power with v d d = 1 .O V. In LL device, from the strict limitation of the stand-by power due to battery operation, Ig must be below 1 mA/cm2 in addition to the I, , * limit. The active power can be reduced from the previous generation by lowering Vdd while maintaining the performance and the stand-by power. SD device includes diverse applications, therefore Ig is relatively relaxed for the compatibility of high performance and low stand-by power. System on a ChipDemands for SOC are increasing from the viewpoint of performance, power, chip size and chip cost. For the 100 nm generation, most of all system LSIs consist of MPU, memory and analog devices. The schematic cross section of the proposed 100 nm generation SOC is shown in Fig. 2, Although there have been several reports about high performance sub-100 nm gate CMOS [2]-[8], most of them are incompatible with high speed eDRAM. In this paper, as a solution for eDRAM, we combine trench capacitor DRAM with high speed CMOS because there are no additional thermal budget after transistor formation, and its performance is as good as that of pure CMOS [9], [lo], [2]. For emerging high speed I/O and mixed signal applications, 1.8V MOSFETs are carefully optimized. On the other hand, 2.5V and 3.3V MOSFETs are still required for eDRAM and I/O (Table 2). For this purpose, triple gate oxid...