A highly manufacturable high density embedded SRAM technology for 90 nm CMOS

Fukaura, Y.; Kasai, K.; Okayama, Y.; Kawasaki, I.; Isobe, K.; Kanda, M.; Ishimaru, K.; Ishiuchi, H.

doi:10.1109/iedm.2002.1175867

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Drowsy Back-bias Scheme1

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“…The cell employs wide bit topology for better cell device mismatch properties [5][6]. The layout of the bitcell is shown in Figure 2.…”

Section: Drowsy Back-bias Schemementioning

confidence: 99%

Low power SRAM techniques for handheld products

Islam

Brand

Lippincott

2005

Proceedings of the 2005 International Symposium on Low Power Electronics and Design - ISLPED '05

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SRAM leakage constitutes a significant portion of the standby power budget of modern SoC products for handheld applications such as PDA and cellular phones. NMOS and PMOS reverse bias techniques for leakage reduction are implemented in a 2MByte SRAM testchip built with low power 90nm technology. Sophisticated analog regulators were implemented to precisely control the PMOS and NMOS reverse bias levels. The application of the reverse bias led to a 16X reduction in total array standby leakage and a cell leakage of only 20pA/bit. Excellent data retention for these bias conditions was demonstrated with detailed Vccmin mesurements.

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“…The cell employs wide bit topology for better cell device mismatch properties [5][6]. The layout of the bitcell is shown in Figure 2.…”

Section: Drowsy Back-bias Schemementioning

confidence: 99%