We study electric-field-dependent charge delocalization from dopant atoms in a silicon junctionless nanowire transistor by low-temperature electron transport measurement. The Arrhenius plot of the temperature-dependent conductance demonstrates the transport behaviors of variable-range hopping (below 30 K) and nearest-neighbor hopping (above 30 K). The activation energy for the charge delocalization gradually decreases due to the confinement potential of the conduction channel decreasing from the threshold voltage to the flatband voltage. With the increase of the source-drain bias, the activation energy increases in a temperature range from 30 K to 100 K at a fixed gate voltage, but decreases above the temperature of 100 K.

We discuss the random dopant effects in long channel junctionless transistor associated with quantum confinement effects. The electrical measurement reveals the threshold voltage variability induced by the random dopant fluctuation. Quantum transport features in Hubbard systems are observed in heavily phosphorus-doped channel. We investigate the single electron transfer via donor-induced quantum dots in junctionless nanowire transistors with heavily phosphorusdoped channel, due to the formation of impurity Hubbard bands. While in the lightly doped devices, one-dimensional quantum transport is only observed at low temperature. In this sense, phonon-assisted resonant-tunneling is suppressed due to misaligned levels formed in a few isolated quantum dots at cryogenic temperature. We observe the Anderson-Mott transition from isolate electron state to impurity bands as the doping concentration is increased.

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We investigated single-electron tunneling through single and coupling dopant-induced quantum dots (QDs) in silicon junctionless nanowire transistor (JNT) by varying temperatures and bias voltages. We observed that two possible charge states of the isolated QD confined in the axis of the initial narrowest channel are successively occupied as the temperature increases above 30 K. The resonance states of the double single-electron peaks emerge below the Hubbard band, at which several subpeaks are clearly observed respectively in the double oscillated current peaks due to the coupling of the QDs in the atomic scale channel. The electric field of bias voltage between the source and the drain could remarkably enhance the tunneling possibility of the single-electron current and the coupling strength of several dopant atoms. This finding demonstrates that silicon JNTs are the promising potential candidates to realize the single dopant atom transistors operating at room temperature.

We investigate gate-regulated transition temperatures for electron hopping behaviours through discrete ionized dopant atoms in silicon junctionless nanowire transistors. We demonstrate that the localization length of the wave function in the spatial distribution is able to be manipulated by the gate electric field. The transition temperatures regulated as the function of the localization length and the density of states near the Fermi energy level allow us to understand the electron hopping behaviours under the influence of thermal activation energy and Coulomb interaction energy. This is useful for future quantum information processing by single dopant atoms in silicon.

We demonstrate transitions of hopping behaviors for delocalized electrons through the discrete dopant-induced quantum dots in n-doped silicon junctionless nanowire transistors by the temperature-dependent conductance characteristics. There are two obvious transition platforms within the critical temperature regimes for the experimental conductance data, which are extracted from the unified transfer characteristics for different temperatures at the gate voltage positions of the initial transconductance g m peak in V g1 and valley in V g2. The crossover temperatures of the electron hopping behaviors are analytically determined by the temperature-dependent conductance at the gate voltages V g1 and V g2. This finding provides essential evidence for the hopping electron behaviors under the influence of thermal activation and long-range Coulomb interaction.

High-density horizontal InAs nanowire transistors are fabricated on the interdigital silicon-on-insulator substrate. Hexagonal InAs nanowires are uniformly grown between face-to-face (111) vertical sidewalls of neighboring Si fingers by metal-organic chemical vapor deposition. The density of InAs nanowires is high up to 32 per group of silicon fingers, namely an average of 4 nanowires per micrometer. The electrical characteristics with a higher on/off current ratio of 2×10 5 are obtained at room temperature. The silicon-based horizontal InAs nanowire transistors are very promising for future high-performance circuits.

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