Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further description of a timing pickoff signal which aligns all of the positioning (spatial channels) pulses in the array is described. The ASIC design is targeted to be scalable with the detector size and flexible to accommodate detectors from different vendors. This paper focuses on circuit implementation issues associated with the design of the ASIC to interface our Phase II MiCES FPGA board with a SiPM array. Moreover, a discussion is provided for strategies to eventually integrate all the analog and mixed-signal electronics with the SiPM, on either a single-silicon substrate or multi-chip module (MCM).
We demonstrate the lithographic fabrication of diffractive optical elements (DOEs) in hybrid SiO2/TiO2 sol-gel glass on 3-D curved surfaces. The concentric circular gratings with periods of 20 μm, 10 μm and 5 μm have been fabricated in sol-gel glass on concave lens by laser direct writing successfully. Continuous 3-Dimensional surface relief with a height of 435 nm, 110 nm and 50 nm has been obtained for the period of 20 μm, 10 μm and 5 μm respectively. The optical test results of the fabricated DOE shows only a little bit deviation from the theoretical calculated results which can be explained by 3-D curved surface effect. We believe this technology can be an effective method to fabricate DOEs with even more complex surface profile on 3-D curved surfaces in terms of its simplicity and cost-effectiveness.
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