2011 IEEE Nuclear Science Symposium Conference Record 2011
DOI: 10.1109/nssmic.2011.6154092
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A CMOS ASIC design for SiPM arrays

Abstract: Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further description of a timing… Show more

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Cited by 11 publications
(8 citation statements)
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“…So, for a SPAD imager, a multiplexing technique must be considered. Analog multiplexing technique could be considered [6]. However the linear circuits used for analog multiplexing are power consuming and thus not compatible for space applications.…”
Section: The Imagermentioning
confidence: 99%
“…So, for a SPAD imager, a multiplexing technique must be considered. Analog multiplexing technique could be considered [6]. However the linear circuits used for analog multiplexing are power consuming and thus not compatible for space applications.…”
Section: The Imagermentioning
confidence: 99%
“…So, for a large array of SPAD, a multiplexing technique must be considered. Analog multiplexing technique could be considered [1]. However, the linear circuits used for analog multiplexing are power consuming.…”
Section: The Imagermentioning
confidence: 99%
“…This ASIC is being designed with the intent of reducing the number of channels between the SiPM array and the backend digital signal processing. A row/column/diagonal summation architecture [8], shown in Fig. 1, helps to reduce the number of channels between the front and backend while producing pulse timing information.…”
Section: Asic Architecturementioning
confidence: 99%
“…The closed loop gain is determined by the ratio of resistors values, thus facilitating the realization of variable gain by modulating the value of R L which is easily done by realizing a switched-resistor array network. Amplifier noise, linearity and bandwidth were optimized to meet the desired performance given in [8]. A simulated input impedance of 70 Ω with a bandwidth of 500 MHz was obtained by doing a tradeoff between the open-loop gain and the dc power consumption.…”
Section: Current Amplifiermentioning
confidence: 99%
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