In this study, we report about the design, fabrication, and operation of a Cu-filled through-silicon via (TSV)-integrated ion trap. TSVs are placed directly underneath electrodes as vertical interconnections between an ion trap and a glass interposer, facilitating the arbitrary geometry design with increasing electrode numbers and evolving complexity. The integration of TSVs reduces the form factor of the ion trap by more than 80%, minimizing parasitic capacitance from 32 ± 2 to 3 ± 0.2 pF. A low RF dissipation is achieved in spite of the absence of the ground screening layer. The entire fabrication process is on a 12-in. wafer and compatible with the established CMOS back end process. We demonstrate the basic functionality of the trap by loading and laser-cooling single 88Sr+ ions. It is found that both the heating rate (17 quanta/ms for an axial frequency of 300 kHz) and lifetime (∼30 min) are comparable with traps of similar dimensions. This work pioneers the development of TSV-integrated ion traps, enriching the toolbox for scalable quantum computing.
Confined by a combination of RF and DC electrical field, trapped ions are well isolated to retain their quantum properties, and laser addressing is used to perform computation and readout [1]. As a promising candidate for quantum computation, ion traps have been developed from mechanically assembled Paul trap to lithography-defined surface electrode ion trap over past two decades. To further boost its computation capability, numerous ions (~100 ions, intermediate scale) should be trapped and entangled simultaneously, which requires the coherent control from thousands of co-planar RF and DC electrodes. This remains a challenge for conventional wire bonding due to the lack of complex signal-feedthrough capability. To resolve this issue, TSVs are integrated into surface electrode ion trap design. At the same time, interposer with redistribution (RDL) layer is introduced for TSV landing. As a result, the CPGA-RDL signal transmission via TSVs can be achieved with much higher flexibility and scalability than wire bonding.
In this study, Silver sintering material is being evaluated on different metal surfaces for high temperature storage and high temperature plus high pressure test up to 300 o C/30kpsi. Three different type of Alumina based ceramic substrates (gold, silver and copper metal finishes) are used as test vehicle in this evaluation. Die attach material and process quality has been evaluated in terms of die shear strength before and after high temperature storage for gold and silver surfaces, further study is the evaluation for the combined test with high temperature and high pressure (HTHP) for plasma treated metal surfaces (silver, gold and copper) and failure mode analysis. Silver-filled epoxy and high temperature epoxy materials are also used as references to make comparison with sintered materials at high temperature storage. After high temperature (300 o C) storage test for 500 hours, shear strength of silver surface samples is increased from average shear strength of 17.96N/mm 2 to 25.97N/mm 2 . However, shear strength of gold surface finished (ENEPIG) samples are decreased drastically from average shear strength of 14.78N/mm 2 to 0.30N/mm 2 . A porous layer is observed at the interfaces near the dense Au/Ag alloy between Ni/Pd/Au finished surface and Ag sintering layer where the interfacial failure mode is happened. High temperature (300 o C) and high pressure (30kpsi) storage test samples for 500 hours shows relatively higher shear strength for both silver surface and ENEPIG surface while degradation happened on the bare copper surface. After combined HPHT test (300 o C/30kpsi/500hours), gold layer in ENEPIG surface is diffused into palladium and nickel layers without creating a porous layer near the Au/Ag alloy and the exhibits good shear strength results which is significantly different behavior from the high temperature storage without pressure. SEM and EDX are used to analyze the cross-sectioned layers after HPHT aging tests. Silver sintering on copper surface shows the lowest shear strength among Ag, Au and Cu substrates. Au substrates has an average shear strength of >20N/mm 2 , which is higher than Ag substrate which has an average shear strength of >10.9N/mm 2 .
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