Polycrystalline (Ba,Sr)(Zr,Ti)O3 thin films sandwiched between two Pt electrodes have been revealed to exhibit hysteretic current-voltage (I-V) characteristics and resistive switching at room temperature. High- and low-resistance states, as well as a less abrupt state transition, occur during the voltage cycle. The maximum ratio between these two resistance states is about 230. Analyses of I-V behaviors have been executed, and it is proposed that space-charge-limited-current conduction in higher voltage region caused by asymmetric electron trapping centers is responsible for such transition of resistance states.

Electrical properties of ( Ba , Sr ) Ti O 3 thin films revisited: The case of chemical vapor deposited films on Pt electrodes High resolution transmission electron microscopy is used to investigate the interfacial layer at interfaces between ͑001͒ ͑Ba, Sr͒TiO 3 ͑BST͒ films and ͑111͒ Pt electrodes. Two distinct types of interfaces are observed. One case is the presence of interfacial layer with distorted structure, whereas another case is the good interfacial match without any interfacial layer. Based on the analyses of crystallographic relationships between BST and Pt, it is proposed that the in-plane lattice structure plays an important role in determining the feature of the interface. The impact of A-O and B-O terminations of BST films on the interfacial layer is also discussed.

Cu barrier seed is a key process in Cu interconnect. Continuous improvement in Cu barrier and seed processes and hardware has enabled improvement in Cu gap fill and effective suppression of Cu diffusion and EM (electron migration). This paper addresses innovations in Cu barrier and seed aimed at suppressing EM. Both barrier and seed processes are crucial for EM qualification. In vias, a robust and continuous barrier reduces Cu diffusion at the interface; robust punch through helps via clean; and the resputtering process can optimize via profile and current distribution. Most early failures in the via could be fixed by the PVD (physical vapor deposition) Ta(N) process. Cu alloy seed was later developed to increase EM life time. CuAl alloy can retard Cu migration at the grain boundary and interface; CuMn alloy can create a self-formed barrier. Co wetting and capping layers are the newest approaches for suppressing EM failures at 32nm and below. The entire Cu line can be encapsulated by a Co layer, leaving no weak spots in the top and sidewall interface and blocking the rapid diffusion path of Cu. Compared to CuMn, the Co solution also offers advantages for gap fill and Rc reduction.

High-κ metal gate is widely used for 32nm and beyond to enable scaling down of MOSFET geometry while improving device speed and gate leakage. This structure requires a good work function metal to tune Vt as well as a stable metal barrier to control inter-diffusion and interaction between the multiple metal gate layers. To meet the integration requirements of metal gate, it is very important to choose the proper metal thin film process. Its stability and excellent integration performance make TiN a good option for metal gate application, but the traditional PVD (physical vapor deposition) TiN process still faces issues, such as plasma damage and poor gap-fill capability. RFPVD (radio frequency physical vapor deposition) TiN has been developed for metal gate application. This paper presents studies of the film texture, density, and inter-diffusion base on different metal gate layers. MOSCAP (metal oxide silicon capacitor) tests showed that RF PVD TiN exhibits low Dit and device leakage. To meet the strict gap-fill requirement of the gate-last scheme, physical gap-fill performance of the high-pressure RF TiN process was checked. It achieved more than 60% bottom coverage and minimal sidewall coverage, allowing the electrode gap-fill window to be effectively enlarged.

For Cu interconnect, Ta(N) barrier is widely used. In this work barrier resputter process was studied. Related wafer acceptance test (WAT), via pouch through, profile of Dual Damascene structure and via electron migration (EM) was investigated. Resputter removes the high resistive Ta(N) from the bottom to lower the via Rc. Barrier first process, including Ta(N) deposition and aggressive resputter, is widely used. Aggressive resputter enlarges top CD of trench and via. That makes gap fill easier and even lower via Rc. Aggressive resputter is helpful to via clean and enhances downstream electro migration (EM) performance. Resputter can change the geometry of dual damascene structure. Such a geometry change has large impact on the upstream electro migration (EM) performance. Barrier resputter also has its shortcoming and limitation. For punch through process, Cu sputtered from the bottom redeposits on the side wall, which may have negative impact on upstream EM performance. Resputter also causes damage to low-k material, with such damage metal line capacitance and reliability may become problem. For Cu interconnect, to manage resputter properly is a key factor to the succeed of back end of line (BEOL).

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The microstructure morphology and evolution of mechanical properties are investigated in this study. The results show that the phases displayed no clear change after thermal exposure at 250 °C for 200 h. The tensile strength of the as-cast alloy showed a downward trend in different degrees with the increase in the tensile temperature, while the influence of elongation was opposite to the tensile strength. In addition, the tensile strength tended to be stable after thermal exposure at 250 °C for 100 h. The main creep mechanism of the as-cast alloy at a low temperature and low stress (T ≤ 250 °C; σ ≤ 40 MPa) is grain-boundary creep. The Monkman–Grant empirical formula was used to fit the relationship between the creep life and the minimum creep rate, and the fitting results are: tr·ε˙min0.95=0.207.

Titanium (Ti) liners have been widely used in ULSI technology to improve contact/via resistance. As devices scale down to 32nm and below, Ti extends its application as a wetting layer for planar metal gate and 3D tri-gate structures. To meet the accompanying challenges, a novel RF/DC PVD chamber was developed, operating with capacitively coupled plasma (CCP) and a DC source to create high metal-ion flux with low energy. The new technology reduces overhang and increases bottom coverage. This paper presents the chamber's tuning knobs that fulfill different process requirements for contact and metal-gate, thereby widening the process window for effective gap fill.