This work studies the use of line-tunnel field effect transistor (Line TFET) devices in analog applications. It presents the DC and small signal characteristics of these devices and compares them with other TFET topologies and with conventional MOSFET technology. The Line-TFET's saturation characteristics are also closely studied, through simulations and experimental characterization, revealing that point tunneling leakage from source to drain not only limits the bias voltage and the gate area but also makes the output conductance independent of the gate length. A common source stage is designed to illustrate and further explore this fact, making comparisons with conventional MOSFET technology. In order to obtain an amplifier with very high voltage gain, a two-stage operational transconductance amplifier is designed considering two different starting points: fixed transistor efficiency (gm/Ids) or fixed normalized current (Ids/W) in order to obtain similar conditions of performance for Line-TFET and MOSFET devices. It is revealed that the Line-TFET design always achieves much higher intrinsic voltage gain (of up to 115 dB) and is more suitable for low power, low frequency applications. Thus, a third design is performed with Line-TFET devices by using gate lengths of 100 nm, achieving 71 dB of open loop voltage gain and 18 nW of power dissipation, which may be suitable for applications such as bio-signal acquisition.
This work addresses the impact of different device parameters on the analog characteristics of Line-Tunneling Field Effect Transistors (Line-TFETs). Source-to-drain separation, pocket thickness, pocket doping, gate-source alignment and the gate length are varied in order to evaluate their impact on the conduction mechanisms and on the overall transfer characteristics of the device. The variation of the main parameters responsible for device variability (pocket thickness and doping and gate-source alignment) is performed in order to analyze their impact on current mirrors, revealing that gate-source overlap improves the analog characteristics of the Line-TFET and that pocket doping should be limited to values smaller than 1018cm-3. Even though the drain current and the transconductance (gm) of this device are proportional to the gate area, simulations compared to experimental data show that the output conductance (gd) of Line-TFETs is practically independent of the gate length. The conduction mechanisms were analyzed through numerical simulations, revealing that this unique characteristic is due to source-to-drain tunneling, which defines the average value of gd on the saturation-like region and does not depend upon the gate length. The impact of this characteristic on analog circuit design is illustrated considering the example of a common-source stage and comparing its design when using MOSFET devices. This example reveals that the designer may choose whether to increase gm or gd in order to increase the circuit gain when using Line-TFETs, fundamentally differing from the MOSFET design.
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