This paper presents the design of low-dropout volt-age regulators (LDO) using nanowire tunnel field-effect tran-sistors (TFETs) and nanowire MOSFET. The devices are mod-eled using lookup tables implemented with experimental measures of TFETs with different source compositions (Si, SiGe and Ge) and MOSFET. In order to compare the designs, the transistors of the differential amplifier in all LDOs is biased with gm/ID = 8 V-1 with a load of 1 μA and 10-pF. It is shown that all TFET based LDOs are stables without the need of a compensator capacitor (CC) even for higher load capacitance. For the MOSFET LDO, a CC of 5-pF capacitor was used. The study shows that the TFET based LDOs deliver higher effi-ciency due to the possibility to operate with low bias current. In the transient analysis it is shown that the TFET LDOs have lower overshoot but higher delay. The Ge-TFET LDO pre-sented settling times for load and line transient close to the MOSFET LDO with 15 μs and 30 μs. The SiGe-TFET LDO shows the best loop gain (60 dB), while the Si-TFET LDO deliv-ers lowest quiescent current (300 pA) and the Ge-TFET have the best GBW (70 KHz) and PSR (-52 dB). It is concluded that the TFET based LDOs can deliver specifications similar or bet-ter than the MOSFET LDO even without the need of CC and with less power consumption.
In this work, hybrid low-dropout voltage regulators (LDO) designed with a TFET-MOSFET nanowire (NW) technologies are presented. The devices were modeled using Verilog-A with lookup tables based on experimental data of NW-TFETs and NW-MOSFETs fabricated in the same silicon vertical process flow. In all LDOs, the amplifier devices were biased with the same gm/ID = 9.5 V-1 for a maximum load current/capacitance of 1 mA/1 nF. In the hybrid regulators, the power transistors are designed with NW-MOSFETs to deliver the high load current, while the other devices are implemented with NW-TFET to provide high gain and low power consumption. Due to different onset voltages, two hybrid LDOs are proposed, one with symmetrical onset voltages implemented with a voltage shift (Hybrid-ΔV LDO) and one with a level-shift stage using the real characteristics of the devices (Hybrid-LS LDO). The hybrid circuits were compared to LDOs designed using only NW-TFETs and with only NW-MOSFETs. The Hybrid-ΔV LDO presents the best loop gain (62 dB) with a low quiescent current (7 nA), while the Hybrid-LS LDO shows a good gain-bandwidth product (700 Hz). In the transient analysis, the hybrid circuits showed a settling time close to the NW-MOSFET
LDO but with higher undershoot/overshoot values in the case of a load transient. As demonstrated, the use of hybrid projects with TFET-MOSFET nanowire technologies enable LDOs with ultra-low power consumption and high loop gain, that are presented on TFET circuits and with a frequency response equivalent of MOSFET circuits.
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