The hole transport material (HTM) free carbon based perovskite solar cells (C-PSCs) are promising for its manufactural simplicity, but they currently suffer from low power conversion efficiencies (PCE) largely because of the voltage loss. Here, a new strategy to increase the PCE by incorporating an ultrathin ferroelectric oxide PbTiO 3 layer between the electron transport material and the halide perovskite is reported. The resulting C-PSCs have achieved PCEs up to 16.37%, which is the highest record for HTM-free C-PSCs to date, mainly ascribable to the ferroelectric layer enhanced open circuit voltage. Detail measurements and analysis show an enhanced built-in potential in the C-PSCs as well as suppression of the non-radiative recombination due to the ferroelectric PbTiO 3 layer incorporation, accounting for the boosted V OC and photovoltaic performance.

Solution‐processed and low‐temperature Sn‐rich perovskites show their low bandgap of about 1.2 eV, enabling potential applications in next‐generation cost‐effective ultraviolet (UV)–visible (vis)–near infrared (NIR) photodetection. Particularly, the crystallization (crystallinity and orientation) and film (smooth and dense film) properties of Sn‐rich perovskites are critical for efficient photodetectors, but are limitedly studied. Here, controllable crystallization for growing high‐quality films with the improvements of increased crystallinity and strengthened preferred orientation through a introducing rubidium cation into the methylammonium Sn‐Pb perovskite system (65% Sn) is achieved. Fundamentally, the theoretical results show that rubidium incorporation causes lower surface energy of (110) plane, facilitating growth in the dominating plane and suppressing growth of other competing planes. Consequently, the methylammonium‐rubidium Sn‐Pb perovskite photodetectors simultaneously achieve larger photocurrent and lower noise current. Finally, highly efficient UV–vis–NIR (300–1100 nm) photodetectors with record‐high linear dynamic range of 110 and 3 dB cut‐off frequency reaching 1 MHz are demonstrated. This work contributes to enriching the cation selection in Sn‐Pb perovskite systems and offering a promising candidate for low‐cost UV–vis–NIR photodetection.

As one of the most promising hole‐transporting materials for perovskite solar cells (PSC), NiO is widely used in the inverted p–i–n cell structure due to its high stability, decent hole conductivity, and easy processability for hysteresis‐free cells. However, the efficiency of NiO‐based PSCs is still low, due largely to the poor perovskite/NiO interface. Herein, a sulfur‐doping strategy to modify NiO surface via ion exchange reaction by a simple and scalable chemical bath deposition technique is introduced, which greatly improves the photovoltaic (PV) performance of the derived devices. A systematic investigation is shown where sulfur doping leads to favorable interfacial energetics with a reduced Voc loss. Sulfur doping at the interface also improves the contact between NiO and perovksite and facilitates the formation of high‐quality perovskite films. Carrier dynamics studies demonstrate reduced defect states and trap‐assisted recombination with sulfur doping, which promote the PV performance of the devices. These merits contribute concurrently to low‐loss charge transfer across the perovskite/NiO interface and facilitate charge transport through the perovskite films, leading to a high champion efficiency of 20.43% of the p–i–n structure solar cell devices.

The deployment of photonic integrated circuits (PICs) necessitates an integration platform that is scalable, high-throughput, cost-effective, and power-efficient. Here we present a monolithic InP on SOI platform to synergize the advantages of two mainstream photonic integration platforms: Si photonics and InP photonics. This monolithic InP/SOI platform is realized through the selective growth of both InP sub-micron wires and large dimension InP membranes on industry-standard (001)-oriented silicon-on-insulator (SOI) wafers. The epitaxial InP is in-plane, dislocation-free, site-controlled, intimately positioned with the Si device layer, and placed right on top of the buried oxide layer to form “InP-on-insulator”. These attributes allow for the realization of various photonic functionalities using the epitaxial InP, with efficient light interfacing between the III–V devices and the Si-based waveguides. We exemplify the potential of this InP/SOI platform for integrated photonics through the demonstration of lasers with different cavity designs including subwavelength wires, square cavities, and micro-disks. Our results here mark a critical step forward towards fully-integrated Si-based PICs.

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Efficient III-V lasers directly grown on Si remain the “holy grail” for present Si-photonics research. In particular, a bufferless III-V laser grown on the Si-photonics 220 nm silicon-on-insulator (SOI) platform could seamlessly bridge the active III-V light sources with the passive Si-based photonic devices. Here we report on the direct growth of bufferless 1.5 µm III-V lasers on industry-standard 220 nm SOI platforms using metal organic chemical vapor deposition (MOCVD). Taking advantage of the constituent diffusivity at elevated growth temperatures, we first devised a MOCVD growth scheme for the direct hetero-epitaxy of high-quality III-V alloys on the 220 nm SOI wafers through synergizing the conventional aspect ratio trapping (ART) and the lateral ART methods. In contrast to prevalent epitaxy inside V-grooved pockets, our method features epitaxy inside trapezoidal troughs and thus enables the flexible integration of different III-V compounds on SOIs with different Si device layer thicknesses. Then, using InP as an example, we detailed the growth process and performed extensive study of the crystalline quality of the epitaxial III-V. Finally, we designed and fabricated both pure InP and InP/InGaAs lasers, and we achieved room-temperature lasing in both the 900 nm band and the 1500 nm band under pulsed optical excitation. Direct epitaxy of these in-plane and bufferless 1.5 µm III-V lasers on the 220 nm SOI platform suggests the imminent interfacing with Si-based photonic devices and the subsequent realization of fully integrated Si-based photonic circuits.

Cation mixing has proved to be effective in stabilizing the high-temperature phase of formamidinium (FA)-based perovskites, affording high-performance n–i–p perovskite solar cells (PSCs).

A compact, efficient and monolithically grown III-V laser source provides an attractive alternative to bonding offchip lasers for Si photonics research. Although recent demonstrations of micro-lasers on (001) Si wafers using thick metamorphic buffers are encouraging, scaling down the laser footprint to nano-scale and operating the nanolasers at telecom wavelengths remain a significant challenge. Here, we report monolithically integrated inplane InP/InGaAs nano-laser array on (001) silicon-oninsulator (SOI) platforms with emission wavelengths covering the entire C-band (1.55 µm). Multiple InGaAs quantum wells are embedded in high-quality InP nanoridges by selective-area growth on patterned (001) SOI. Combined with air-surrounded InP/Si optical cavities, room-temperature operation at multiple telecom bands is obtained by defining different cavity lengths with lithography. The demonstration of telecom-wavelength monolithic nano-lasers on (001) SOI platforms presents an important step towards fully integrated Si photonics circuits.