Plasmas, known to emit high levels of vacuum ultraviolet (VUV) radiation, are used in the semiconductor industry for processing of low-k organosilicate glass (SiCOH) dielectric device structures. VUV irradiation induces photoconduction, photoemission, and photoinjection. These effects generate trapped charges within the dielectric film, which can degrade electrical properties of the dielectric. The amount of charge accumulation in low-k dielectrics depends on factors that affect photoconduction, photoemission, and photoinjection. Changes in the photo and intrinsic conductivities of SiCOH are also ascribed to the changes in the numbers of charged traps generated during VUV irradiation. The dielectric-substrate interface controls charge trapping by affecting photoinjection of charged carriers into the dielectric from the substrate. The number of trapped charges increases with increasing porosity of SiCOH because of charge trapping sites in the nanopores. Modifications to these three parameters, i.e., (1) VUV induced charge generation, (2) dielectric-substrate interface, and (3) porosity of dielectrics, can be used to reduce trappedcharge accumulation during processing of low-j SiCOH dielectrics. Photons from the plasma are responsible for trapped-charge accumulation within the dielectric, while ions stick primarily to the surface of the dielectrics. In addition, as the dielectric constant was decreased by adding porosity, the defect concentrations increased. V
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The microstructure of Cu interconnects fabricated with Ta and Co liner materials had been examined by transmission electron microscopy and correlated to the electrical characteristics. Cu lines of 40 nm width were fabricated on 300 mm Si wafers by conventional CMOS backend processing. Electrical measurements performed immediately after fabrication of these Cu lines showed similar electrical resistance for Co and Ta liners. However, a 2.5-hour anneal at 375°C led to 5% more resistance reduction for Cu lines with the Ta liner than with the Co liner. Microstructure analyses showed that Cu lines with the Ta liner had 24% coherent Σ3 grain boundaries while lines with the Co liner yielded only 6% of coherent grain boundaries. In addition, Cu with Ta liner had a stronger 〈111〉 texture along the line width direction. However, the overall grain size distribution was similar between Ta and Co liners. These results suggest Co liner has some impact on Cu microstructures, which may be a root cause for the relatively higher line resistance.
Scaling the BEOL into 14nm includes challenges in both the material selection and the integration. Metallization-induced degradation of the ULK is an issue regardless of dielectric choice, or the PVD vs. ALD selection, and options for possible recovery of characteristics are numerous. In barrier/liner/seed decisions, the integration choices play into material selection, and the deposition technique's impact upon microstructure, and hence reliability, is significant. For plating, conventional processes may not allow the high fill speeds necessary, and aspect ratio constraints are driving processes to new areas. Finally, we will also address how CPI is changing as interconnect evolves.
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