and PMOS (AQi is negligible. However, AVfb does not reach OV We report here for the first time that Fermi pinning at the because Si-Hf and Si-0-Hf bonds co-exist at the polySi interface. The polySilmetal oxide interface causes high threshold voltages in AVfb saturation value depends only on the bond number ratio. A MOSFET devices. Results indicate that pinning occurs due to the comparison of AVfb for HfOz (ALD or MOCVD) and HfSixOy interfacial Si-Hf and Si-0-AI bonds for HfO, and AIzO,, respectively. (MOCVD) films deposited with different precursors and dopant This fundamental characteristic also affects the observed polySi activation anneals produce, the universal curve in Fig. 11. The slight depletion. Device data and simulation results will be presented. variation in AVb for Hf02 can be attributed to differences in Keywords: Hf02, AI203, Fermi pinning, polYd, gate dielectric. processing conditions. Our data indicates that the shifts of Vfb(n+) INTRODUCTION and Vfb(pt) from the characteristic values for SiO, NMOS and Scaling MOSFETs to improve performance results in PMOS are a fundamental characteristic of the PolySilMeOx interface. higher gate leakage as the SiOz gate melectic becomes thinner. To These shifts are responsible for the observed high Vts. address this issue, there has been much interest in hafnium-based The impact of the sub-monolayer HfOz on the CETacc is dielectrics as a potential gate dielectric [1-3]. Two major issues shown in Figs. 12 and 13. Although the p+ gate CETacc increases evident in numerous publications [1-3] that must be addressed to with each subsequent cycle, the n+ gate has a CETacc minimum at IO fabricate useful devices for CMOS circuit applications are (1) the cycles, The n+ gate is in depletion and the minimum indicates Si-Hf high threshold voltages and (2) the large CETinv difference between bonds reduce the polySi depletion. To investigate this further, CMOS NMOS and PMOS. To date, a PolySiIMeOx CMOS process with devices were fabricated (Fig. 14). The polySi depletion for ntgate acceptable Vts for both NMOS and PMOS has not been reported. NMOS (p+ gate PMOS) is decreased (increased) when SiOz is capped Defects and charge within the gatestack (Fig. I ) can result with HfO,. This tradeoff in polySi depletion is attributed to Fermi in substantial Vt shifts. At the top interface, Fermi pinning is a pinning near (Fig. 8). Less band bending occurs for n+ polySi mechanism known to cause high Vts for metal gates [41. Considering because the polySi interface is pinned close to the bulk polySi Fermi the polySi/MeOx interface shown in Fig. 2, the question arises, 'Are level. For p+ gates, more band bending occurs because the interface is the metal atoms at the interface part of the dielectric or part of the pinned further away from the bulk. This effect occurs for low and gate electrode?' This raises the issue as to whether the interface bonds high temperame activation anneals (Fig. 15). This effect is the likely affect the Vt. In this work, we examine the role of the polySiIMeOx cause...
The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore's law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors.
Polycrystalline-silicon (poly-Si) gate compatibility issues with HfO2 and Al2O3 capped HfO2 gate dielectrics are reported. It can be generally stated that chemical vapor deposition (CVD) silicon gates using silane deposited directly onto HfO2 results in electrical properties much worse compared to similar HfO2 films using platinum metal gates. However, depositing CVD silicon gates directly onto Al2O3 capped HfO2 showed greater than a 104 times reduction in gate leakage compared to the poly-Si/HfO2 and poly-Si/SiO2 controls of similar electrical thickness.
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