Oxynitride films grown on preoxidized (100) silicon surfaces in a nitric oxide (NO) ambient at 950 °C have been investigated using x-ray photoelectron spectroscopy (XPS), secondary ion mass spectrometry (SIMS), atomic force microscopy (AFM), and cross-sectional transmission electron microscopy (XTEM). Compared to N2O oxynitride, NO oxynitride exhibits very different surface chemistry, interface properties, and growth mechanisms. The etch back of NO and N2O oxynitride films allows control of sample thickness for the XPS measurements. NO oxynitride has the interfacial nitrogen (Nint) sharply peaked on the Si substrate side of the interface, while it is broad and on the dielectric side of the interface for the N2O oxynitride. The N(1s) XPS results reveal a clear distinction between N2O oxynitride and NO oxynitride. Near the Si/dielectric interface the NO oxynitride shows primarily Si≡N bonds, while the N2O films showed a N(1s) binding energy peak that is in-between that of Si≡N bonds and Si2=N—O bonds. Furthermore, the NO oxynitride surface roughness as determined by AFM is lower than that of the Si/SiO2 interface.

The direct growth of hexagonal boron nitride (h-BN) by industrially scalable methods is of broad interest for spintronic and nanoelectronic device applications. Such applications often require atomically precise control of film thickness and azimuthal registry between layers and substrate. We report the formation, by atomic layer epitaxy (ALE), of multilayer h-BN(0001) films (up to 7 monolayers) on Co(0001). The ALE process employs BCl3/NH3 cycles at 600 K substrate temperature. X-ray photoelectron spectroscopy (XPS) and low energy electron diffraction (LEED) data show that this process yields an increase in h-BN average film thickness linearly proportional to the number of BCl3/NH3 cycles, with BN layers in azimuthal registry with each other and with the Co(0001) substrate. LEED diffraction spot profile data indicate an average BN domain size of at least 1900 Å. Optical microscopy data indicate the presence of some domains as large as ∼20 μm. Transmission electron microscopy (TEM) and ambient exposure studies demonstrate macroscopic and microscopic continuity of the h-BN film, with the h-BN film highly conformal to the Co substrate. Photoemission data show that the h-BN(0001) film is p-type, with band bending near the Co/h-BN interface. Growth of graphene by molecular beam epitaxy (MBE) is observed on the surface of multilayer h-BN(0001) at temperatures of 800 K. LEED data indicate azimuthal graphene alignment with the h-BN and Co(0001) lattices, with domain size similar to BN. The evidence of multilayer BN and graphene azimuthal alignment with the lattice of the Co(0001) substrate demonstrates that this procedure is suitable for scalable production of heterojunctions for spintronic applications.

IntroductionA high performance 0.20pm logic technology has been developed with six levels of planarized copper interconnects. 0.15pm transistors (Lg,,,=0.15+0.04pm) are optimized for 1.8V operation to provide high performance with low power-delay products and excellent reliability. Copper has been integrated into the back-end to provide low resistance interconnects. Critical layer pitches for the technology are summarized in Table 1 and enable fabrication of 7.6pm2 6T SRAM cells.Isolation and Transistors CMP planarized shallow trenches with good electrical isolation down to n+/p+ spacings of 0.5pm were fabricated (Fig. 1). Dual gate 0.15pm transistors with 35A physical gate oxides (accumulation t,,=39A measured at Vg=+l .SV) were formed using super steep retrograde channels, shallow extensions and halos, relatively deep source/drain regions and 1 OOnm nitride spacers. CoSi, was selectively formed on the polysilicon gates and source/drain regions with a nominal sheet resistance of 9Wsq. Rapid thermal processing was utilized as much as possible throughout the flow to minimize transient enhanced dopant diffusion.Fig. 2 shows a typical SEM cross-section of a NMOS transistor with a gate length of 0.15pm. Well delineated shallow S/D extensions and the deeper S/D junctions are clearly observed. The saturation drive currents for nominal gate length NMOS and PMOS devices are shown in Fig. 3 . The nominal drive currents are 630pNpm for NMOS and 230pA/ym for PMOS at 1.8V. The off-state leakage currents of these devices are well below the worst case leakage specification of 2nA/pm. The drain induced barrier lowering (DIBL) measured on NMOS and PMOS devices is plotted as a function of Leff in Fig. 4. Good short channel characteristics are maintained down to effective channel lengths of O.1ym. The Vt roll-off for N and P devices in the linear and saturation regions are shown in Fig. 5. The Vt's are 0.44V and -0.46V for Nch and Pch respectively, at a gate length of 0.15pm and the associated subthreshold slopes are less than 90mv/dec. The use of nitrided gate oxides was investigated due to their superior hot carrier reliability. Fig. 6 compares the degradation under hot carrier stress of nitrided oxides to thermal oxides and highlights the improved reliability of NO-annealed oxides. Peak Gms comparable to those from thermal oxides were obtained (Fig. 7). A further advantage afforded by nitrided gate dielectrics is its superior boron blocking properties, Increasing the poly silicon doping in the P+ gate to reduce poly depletion resulted in only a 88mV Vt shift in nitrided oxides (Fig. 8) compared to a 300mV Vt shift in thermal oxides. A significant reduction in the inversion to, is achieved with the higher gate doping, resulting in improved device characteristics. NMOS transistor design focused on minimizing defect enhanced dopant re-distribution such as TED. To this end, the effect of different source/drain implant energies on NMOS transistor performance is shown in Fig. 9. The lower energy implant results in a significantl...

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