A high performance 1.8 V, 0.20 μm CMOS technology with copper metallization

Abstract

IntroductionA high performance 0.20pm logic technology has been developed with six levels of planarized copper interconnects. 0.15pm transistors (Lg,,,=0.15+0.04pm) are optimized for 1.8V operation to provide high performance with low power-delay products and excellent reliability. Copper has been integrated into the back-end to provide low resistance interconnects. Critical layer pitches for the technology are summarized in Table 1 and enable fabrication of 7.6pm2 6T SRAM cells.Isolation and Transistors CMP planarized shallow trenches with good electrical isolation down to n+/p+ spacings of 0.5pm were fabricated (Fig. 1). Dual gate 0.15pm transistors with 35A physical gate oxides (accumulation t,,=39A measured at Vg=+l .SV) were formed using super steep retrograde channels, shallow extensions and halos, relatively deep source/drain regions and 1 OOnm nitride spacers. CoSi, was selectively formed on the polysilicon gates and source/drain regions with a nominal sheet resistance of 9Wsq. Rapid thermal processing was utilized as much as possible throughout the flow to minimize transient enhanced dopant diffusion.Fig. 2 shows a typical SEM cross-section of a NMOS transistor with a gate length of 0.15pm. Well delineated shallow S/D extensions and the deeper S/D junctions are clearly observed. The saturation drive currents for nominal gate length NMOS and PMOS devices are shown in Fig. 3 . The nominal drive currents are 630pNpm for NMOS and 230pA/ym for PMOS at 1.8V. The off-state leakage currents of these devices are well below the worst case leakage specification of 2nA/pm. The drain induced barrier lowering (DIBL) measured on NMOS and PMOS devices is plotted as a function of Leff in Fig. 4. Good short channel characteristics are maintained down to effective channel lengths of O.1ym. The Vt roll-off for N and P devices in the linear and saturation regions are shown in Fig. 5. The Vt's are 0.44V and -0.46V for Nch and Pch respectively, at a gate length of 0.15pm and the associated subthreshold slopes are less than 90mv/dec. The use of nitrided gate oxides was investigated due to their superior hot carrier reliability. Fig. 6 compares the degradation under hot carrier stress of nitrided oxides to thermal oxides and highlights the improved reliability of NO-annealed oxides. Peak Gms comparable to those from thermal oxides were obtained (Fig. 7). A further advantage afforded by nitrided gate dielectrics is its superior boron blocking properties, Increasing the poly silicon doping in the P+ gate to reduce poly depletion resulted in only a 88mV Vt shift in nitrided oxides (Fig. 8) compared to a 300mV Vt shift in thermal oxides. A significant reduction in the inversion to, is achieved with the higher gate doping, resulting in improved device characteristics. NMOS transistor design focused on minimizing defect enhanced dopant re-distribution such as TED. To this end, the effect of different source/drain implant energies on NMOS transistor performance is shown in Fig. 9. The lower energy implant results in a significantl...

Multilayer interconnect technology for scaling

“…Because the vapor pressure of the Cu halide used as the etching material is low, Cu dry etching for realizing Cu interconnect of the cutoff type requires heating of the slab to a high temperature, which makes realization difficult because the photoresist lacks heat resistance. As a consequence, the damascene interconnect structure (first used in Damascus in ancient Syria), in which a groove in a plate is filled with metal, was developed [8,9]. This old technology, called zogan in Japanese, became a breakthrough in interconnect technology.…”

“…To make this damascene structure practical for multilayer interconnects extending through more than six layers, the number of manufacturing processes must be reduced. For this purpose, a technology called dual damascene, in which the holes and interconnect trenches are simultaneously formed to join the upper and lower layer interconnects, and are simultaneously filled, was developed [8,9]. In order to use Cu plating as a method of placing Cu interconnects in oxidation film trenches on silicon wafers, a Cu film must be deposited in advance by sputtering as a seed layer.…”

Inductive properties of high-performance power distribution grids

“…The inductive portion of the impedances is relatively insensitive to the interconnect resistivity in the range of 1.7 cm to 2.5 cm (typical for advanced processes with copper interconnect [24], [25], [26]). A conductivity of 40 S/ m (2.5 cm) yields an inductance that is less than 4% larger than the inductance obtained for a conductivity of 58 S/ m.…”

Modeling and characterization of copper interconnects for SoC design

“…These variations result in variation of the signal delay and crosstalk noise. New processes such as Cu dual damascene and chemical mechanical polishing (CMP) further complicate the design [2]. The worst-case simulation is no longer adequate, and the traditional practice of using excessive performance guard band affects product margin, even profit.…”