Modeling and characterization of copper interconnects for SoC design

Abstract

Interconnect (wiring) is central to nanometer system-on-a-chip (SoC) design. As such, accurate interconnect modeling and characterization are key to the design and verification of SoCs. Today copper (Cu) has become a mainstream material for on-chip interconnections. Unlike aluminum (Al) interconnects, Cu wire line width and thickness is a function of wire width and spacing, wire-pattern density, and topography. These new effects must be modeled accurately for designs to achieve first-time silicon success. In this paper we discusses the Cu process and its impact on modeling the interconnect parasitic elements -resistance (R), capacitance (C), and inductance (L). For a given process node, use of Cu reduces interconnect delay and power, but from a design prospective, the same effect is achieved by reducing wire length. Impact of the X-Architecture, which makes pervasive use of diagonal lines and has the promise of reducing wire length to an average of 20%, is also discussed. Finally, silicon validation of interconnect R,C, and L model using a test-chip approach is covered.

Toward quantifying the IC design value of interconnect technology improvements

“…We implement designs using TSMC 45nm LVT and HVT libraries, with eight metal layers (M1, M2, ..., M8). Synthesis is performed using Synopsys Design Compiler vG-2012.06 [15], 1 and placement and routing (P&R) using Synopsys IC Compiler vG-2012.06-ICC-SP3 [16]. We also use Synopsys IC Compiler for timing and power analysis.…”

“…To quantify the quality of improved interconnect technology, conventional studies mostly focus on modeling and characterization of R and C values corresponding to a given (new) process technology [1] [8] [9] [11] [12] [13]. However, nominal RC improvements do not match actual block-or chip-level benefits in terms of design metrics such as circuit performance, power and area.…”

Comprehensive Performance Analysis of Interconnect Variation by Double and Triple Patterning Lithography Processes

“…Unlike a lift-off process in Al, a Cu damascene process requires the etching of a trench first and then the depositing of Cu. As a result, the cross section of the metal assumes a trapezoidal shape rather than a rectangular shape [24][25][26]. Nonvertical sidewalls of metal conductors can usually be modeled with a nonzero sidewall or tapering angles [24,25,27].…”

“…As a result, the cross section of the metal assumes a trapezoidal shape rather than a rectangular shape [24][25][26]. Nonvertical sidewalls of metal conductors can usually be modeled with a nonzero sidewall or tapering angles [24,25,27]. For simplicity, the bottom width is set to 6 nm narrower than the top width of the metal (the tapering angle q is approximately 3 o ).…”

Simulation of Lithography-caused Gate Length and Interconnect Linewidth Variational Impact on Circuit Performance in Nanoscale Semiconductor Manufacturing

“…In the nano-and GHz-era, interconnect is a big issue [1] and scaling increases the systematic intra-die CD variation [2]. One major source of CD variation is the optical lithography process [3], including the proximity effect, Coma, lens aberrations, and flare.…”