Toward quantifying the IC design value of interconnect technology improvements

Chan, Theodore; Kahng, Andrew B.; Li, Jiajia

doi:10.1109/slip.2013.6681680

Cited by 2 publications

(2 citation statements)

References 9 publications

(12 reference statements)

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“…Since our N7 technology is missing detailed BEOL stack information which is necessary for design enablement, we scale up the N7 library cells' dimensions to use an N28 BEOL stack, following the methodology described in Han et al 5 ¶ . The methodology described by Chan et al 1 is used to derive the missing resistance (R) and capacitance (C) information for N7 BEOL from original N28 wire RC values. Here, R (C) is defined as per unit-length resistance (capacitance) in a specific foundry node.…”

Section: Methodsmentioning

confidence: 99%

ILP-based co-optimization of cut mask layout, dummy fill, and timing for sub-14nm BEOL technology

et al. 2015

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Self-aligned multiple patterning (SAMP), due to its low overlay error, has emerged as the leading option for 1D gridded back-end-of-line (BEOL) in sub-14nm nodes. To form actual routing patterns from a uniform "sea of wires", a cut mask is needed for line-end cutting or realization of space between routing segments. Constraints on cut shapes and minimum cut spacing result in end-of-line (EOL) extensions and non-functional (i.e. dummy fill) patterns; the resulting capacitance and timing changes must be consistent with signoff performance analyses and their impacts should be minimized.In this work, we address the co-optimization of cut mask layout, dummy fill, and design timing for sub-14nm BEOL design. Our central contribution is an optimizer based on integer linear programming (ILP) to minimize the timing impact due to EOL extensions, considering (i) minimum cut spacing arising in sub-14nm nodes; (ii) cut assignment to different cut masks (color assignment); and (iii) the eligibility to merge two unit-size cuts into a bigger cut. We also propose a heuristic approach to remove dummy fills after the ILP-based optimization by extending the usage of cut masks. Our heuristic can improve critical path performance under minimum metal density and mask density constraints.In our experiments, we study the impact of number of cut masks, minimum cut spacing and metal density under various constraints. Our studies of optimized cut mask solutions in these varying contexts give new insight into the tradeoff of performance and cost that is afforded by cut mask patterning technology options. * According to 2015 ITRS reports, 6 the lithography "cliff" for 2D shapes (e.g., cut) is approximately 110nm. † N10 (resp. N7) is foundry nomenclature for "10nm node" (resp. "7nm node"), just as foundry nomenclature for the first foundry FinFET node (with minimum metal pitch = 64nm) was N14 (Samsung, GLOBALFOUNDRIES) or N16 (TSMC).

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Section: Methodsmentioning

confidence: 99%

ILP-based co-optimization of cut mask layout, dummy fill, and timing for sub-14nm BEOL technology

et al. 2015

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“…3 To derive the missing 7nm wire RC information from 28nm RC values, we scale up R by 15× for 7nm wire R, and use the same wire C value. This follows methodology of, e.g., [4] to account for the rapid increase of resistivity in advanced nodes. Then, since we are using the scaled geometries to mimic a 7nm P&R flow, R and C per unit length are scaled down (in the P&R tool) by 2.5×.…”

Section: Physical Implementation With Advanced Technologymentioning

confidence: 99%

Evaluation of BEOL design rule impacts using an optimal ILP-based detailed router

Han

Kahng

Lee

2015

Proceedings of the 52nd Annual Design Automation Conference

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Continued technology scaling with more pervasive use of multipatterning has led to complex design rules and increased difficulty of maintaining high layout densities. Intuitively, emerging constraints such as unidirectional patterning or increased via spacing will decrease achievable density of the final place-and-route solution, worsening die area and product cost. However, no methodology exists for accurate assessment of design rules' impact on physical chip implementation. At the same time, this is a crucial need for early development of BEOL process technologies, particularly with FinFET or future vertical-device architectures where cell footprints can become much smaller than in bulk planar CMOS technologies. In this work, we study impacts of patterning technology choices and associated design rules on physical implementation density, with respect to cost-optimal design rule-correct detailed routing. A key contribution is an Integer Linear Programming (ILP) based optimal router (OptRouter) which considers complex design rules that arise in sub-20nm process technologies. Using OptRouter, we assess wirelength and via count impacts of various design rules (implicitly, patterning technology choices) by analyzing optimal routing solutions of clips (i.e., switchbox instances) extracted from post-detailed route layouts in an advanced technology.

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Toward quantifying the IC design value of interconnect technology improvements

Cited by 2 publications

References 9 publications

ILP-based co-optimization of cut mask layout, dummy fill, and timing for sub-14nm BEOL technology

ILP-based co-optimization of cut mask layout, dummy fill, and timing for sub-14nm BEOL technology

Evaluation of BEOL design rule impacts using an optimal ILP-based detailed router

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