Multilayer interconnect technology for scaling

Abstract

SUMMARYWith the miniaturization of silicon ultralarge-scale integrated circuits (ULSI), the increase in interconnect delay exceeds the delay time of the transistors, and the interconnect begins to control the performance of the entire ULSI chip. To enhance further the speed of ULSI, it is necessary to solve the problem of large-distance propagation of high-speed signals in the large-scale chip. The damascene multilayer interconnect integration technology is an important interconnect technology for achieving large-scale integration and high speed in ULSI at low cost. CMP technology, Cu electroplating technology, and lowdielectric-constant insulating film layers are described as element process technologies required for its implementation.

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“…The decrease in the design rule of ultra-large-scale integrated circuits below the submicron level causes difficulties in fabrication with conventional materials [73,74]. For example, if silicon oxide and aluminium are used in the interconnection stack with a small design rule, the resistance-capacitance time delay is not negligible compared with the switching time delay in each transistor [75,76].…”