Inductive properties of high-performance power distribution grids

Mezhiba, Andrey V.; Friedman, Eby G.

doi:10.1109/tvlsi.2003.808683

Cited by 63 publications

(21 citation statements)

References 31 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Therefore, orthogonal lines can be evaluated independently [6]. Mesh lines in one direction only affect the mesh inductance in the same direction.…”

Section: ⅱ Modeling Proceduresmentioning

confidence: 99%

Modeling of an On-Chip Power/Ground Meshed Plane Using Frequency Dependent Parameters

Hwang¹,

Kim²,

Pak³

et al. 2011

Journal of electromagnetic engineering and science

View full text Add to dashboard Cite

This paper proposes a new modeling method for estimating the impedance of an on-chip power/ground meshed plane. Frequency dependent R, L, and C parameters are extracted based on the proposed method so that the model can be applied from DC to high frequencies. The meshed plane model is composed of two parts: coplanar multi strip (CMS) and conductor-backed CMS. The conformal mapping technique and the scaled conductivity concept are used for accurate modeling of the CMS. The developed microstrip approach is applied to model the conductor-backed CMS. The proposed modeling method has been successfully verified by comparing the impedance of RLC circuit based on extracted parameters and the simulated impedance using a 3D-field solver. Ⅰ. IntroductionRecently, communication, computing, and sensing systems have incorporated noise-sensitive analog RF circuits, and noisy digital circuits into a single chip/package for small form factors and high performance. In this type of mixed-mode system, however, the simultaneous switching noise (SSN) caused by high-speed digital circuits not only affects digital functionality but also degrades the receiver sensitivity and reliability of neighboring analog and RF circuits [1], [2].The amount of SSN is determined by the amount of current consumption of the circuits and the impedance profile of the power distribution network (PDN) seen from the circuits. An efficient way to reduce the amount of SSN is to design a PDN that has low impedance at the switching frequency and its harmonics. Therefore, estimation of the impedance properties of the PDN is important for the reliable operation of the system. As the operating frequency exceeds GHz levels, the highfrequency performance of the PDN should also be taken into consideration.For on-chip PDNs in high-speed systems, a meshed plane, as shown in Fig. 1, has been widely adopted because of its low inductance. The on-chip power/ground meshed plane has been extensively analyzed [3]～ [5]. However, it is difficult to apply previous works to meshed planes that are fabricated with standard CMOS processes because they are not compatible with the SPICE Fig. 1. Conventional on-chip power/ground meshed plane composed of two metal layers.simulator [3]. They are also not suitable for a standard CMOS process because of the vertical configurations; the metal thickness and the dielectric layer stack-up are different. Consequently, the applicable frequency range of the works is limited to a very narrow frequency range in a standard CMOS process [4], [5]. This paper provides details about the modeling of an on-chip meshed plane on low-resistivity silicon substrates. Quasi-static analysis using conformal mapping and the scaled conductivity concept are applied to calculate the frequency dependent parameters of the coplanar multi strip (CMS) structure. For a conductor-backed CMS, the developed microstrip approaches are simplified to suit the physical dimensions of the targeted structure and are applied to extract parameters. The impedance profiles of the...

show abstract

“…Therefore, orthogonal lines can be evaluated independently [6]. Mesh lines in one direction only affect the mesh inductance in the same direction.…”

Section: ⅱ Modeling Proceduresmentioning

confidence: 99%

Modeling of an On-Chip Power/Ground Meshed Plane Using Frequency Dependent Parameters

Hwang¹,

Kim²,

Pak³

et al. 2011

Journal of electromagnetic engineering and science

View full text Add to dashboard Cite

show abstract

“…Increasing the parasitic resistance of a decoupling capacitor is limited by the target impedance of the power distribution system. Decreasing the inductance of a power distribution system is highly desirable and, if properly designed, the inductance of a power distribution system can be significantly reduced [16].…”

Section: Dependence Of Impedance On Power Distribution System Paramentioning

confidence: 99%

Decoupling Capacitors for Multi-Voltage Power Distribution Systems

Jakushokas

Popovich

Mezhiba

et al. 2010

Power Distribution Networks With on-Chip Decoupling Capacitors

View full text Add to dashboard Cite

Abstract-Multiple power supply voltages are often used in modern high-performance ICs, such as microprocessors, to decrease power consumption without affecting circuit speed. To maintain the impedance of a power distribution system below a specified level, multiple decoupling capacitors are placed at different levels of the power grid hierarchy. The system of decoupling capacitors used in power distribution systems with multiple power supplies is described in this paper. The noise at one power supply can propagate to the other power supply, causing power and signal integrity problems in the overall system. With the introduction of a second power supply, therefore, the interaction between the two power distribution networks should be considered.The dependence of the impedance and magnitude of the voltage transfer function on the parameters of the power distribution system is investigated. An antiresonance phenomenon is intuitively explained in this paper. It is shown that the magnitude of the voltage transfer function is strongly dependent on the parasitic inductance of the decoupling capacitors, decreasing with smaller inductance. Design techniques to cancel and shift antiresonant spikes out of range of the operating frequencies are presented. It is also shown that it is highly desirable to maintain the effective series inductance of the decoupling capacitors as low as possible to decrease the overshoots of the response of the dual-voltage power distribution system over a wide range of operating frequencies. A criterion for an overshoot-free voltage response is presented in this paper. It is noted that the frequency range of the overshoot-free voltage response can be traded off with the magnitude of the response.

show abstract

“…Therefore, a maximum power pitch should be carefully chosen such that the low impedance current return paths are still maintained at the full-chip level but with reasonable routing area. How to choose such a maximum power pitch constraints has been addressed in [16,23,14]. Therefore, a power network can be designed with a maximum power pitch constraint (P GP ) such that as long as its power pitch is less than P GP , the resulting power network is guaranteed to satisfy the required IR-drop, Ldi/dt and electromigration constraints.…”

Section: Power Pitch and Signal Shielding Constraintsmentioning

confidence: 99%