Modeling of an On-Chip Power/Ground Meshed Plane Using Frequency Dependent Parameters

Abstract

This paper proposes a new modeling method for estimating the impedance of an on-chip power/ground meshed plane. Frequency dependent R, L, and C parameters are extracted based on the proposed method so that the model can be applied from DC to high frequencies. The meshed plane model is composed of two parts: coplanar multi strip (CMS) and conductor-backed CMS. The conformal mapping technique and the scaled conductivity concept are used for accurate modeling of the CMS. The developed microstrip approach is applied to model the conductor-backed CMS. The proposed modeling method has been successfully verified by comparing the impedance of RLC circuit based on extracted parameters and the simulated impedance using a 3D-field solver. Ⅰ. IntroductionRecently, communication, computing, and sensing systems have incorporated noise-sensitive analog RF circuits, and noisy digital circuits into a single chip/package for small form factors and high performance. In this type of mixed-mode system, however, the simultaneous switching noise (SSN) caused by high-speed digital circuits not only affects digital functionality but also degrades the receiver sensitivity and reliability of neighboring analog and RF circuits [1], [2].The amount of SSN is determined by the amount of current consumption of the circuits and the impedance profile of the power distribution network (PDN) seen from the circuits. An efficient way to reduce the amount of SSN is to design a PDN that has low impedance at the switching frequency and its harmonics. Therefore, estimation of the impedance properties of the PDN is important for the reliable operation of the system. As the operating frequency exceeds GHz levels, the highfrequency performance of the PDN should also be taken into consideration.For on-chip PDNs in high-speed systems, a meshed plane, as shown in Fig. 1, has been widely adopted because of its low inductance. The on-chip power/ground meshed plane has been extensively analyzed [3]～ [5]. However, it is difficult to apply previous works to meshed planes that are fabricated with standard CMOS processes because they are not compatible with the SPICE Fig. 1. Conventional on-chip power/ground meshed plane composed of two metal layers.simulator [3]. They are also not suitable for a standard CMOS process because of the vertical configurations; the metal thickness and the dielectric layer stack-up are different. Consequently, the applicable frequency range of the works is limited to a very narrow frequency range in a standard CMOS process [4], [5]. This paper provides details about the modeling of an on-chip meshed plane on low-resistivity silicon substrates. Quasi-static analysis using conformal mapping and the scaled conductivity concept are applied to calculate the frequency dependent parameters of the coplanar multi strip (CMS) structure. For a conductor-backed CMS, the developed microstrip approaches are simplified to suit the physical dimensions of the targeted structure and are applied to extract parameters. The impedance profiles of the...

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“…For the capacitance estimation, the Schwarz-Christoffel transformation, which is a conformal transformation to transform the upper half-plane onto the interior of a simple polygon [15], is used. Through the Schwarz-Christoffel transformation, we can estimate the capacitance of the TL sections given their PMC boundary condition by transforming the partitions of the TL sections into the parallel plate [15]. Then, we can easily estimate their capacitance by the capacitance equation for two parallel plates, including a dielectric material between them.…”

“…All RLGC values obtained from ) of section A x . In the condition that the space (S 1 ) is wide and W 1 » H ILD , the supported coplanar waveguide can be considered to be a microstrip line [15]. Therefore, the air-filled capacitance (C air-filled Ax ) of section A x is calculated by (2) [15], which is the equation for the capacitance caused by all faces (top face, bottom face, and two side faces) of the microstrip line obtained from the conformal mapping-based empirical approach…”

“…First, we calculate the air-filled capacitance (C air-filled C air-filled upper is the air-filled capacitance caused by the electric fields between the tops of the P/G line bounded by PMC in section B x . The capacitance is calculated by (12) [15] …”

“…The geometric factor of section B x is obtained from the derivative of the external inductance (L ext(Bx) ), as presented in (15) …”

“…To calculate C upper , we calculate the capacitance (C upper(IMD) ) of the height H IMD2 according to (18) [15] ς = ((exp(P 2 π/(2H I M D2 ))/2 − 1)/ ((exp(P 2 π/(2H IMD2 ))/2 + 1)) 2 (18a)…”