Interposer Power Distribution Network (PDN) Modeling Using a Segmentation Method for 3-D ICs With TSVs

Abstract

In this paper, we propose models for large-sized silicon interposer power distribution networks (PDNs) and through silicon via (TSV)-based stacked grid-type PDNs using a segmentation method. We model the PDNs as distributed scalable resistance (R), inductance (L), conductance (G), and capacitance (C)-lumped models for an accurate estimation of the PDN impedance, including PDN inductance and wave phenomena such as the mode resonance at the high end of the frequency range. For this estimation, it is necessary to accurately model all transmission line (TL) sections that form the PDNs using a conformal mapping method and a phenomenological loss equivalence method (PEM). After modeling the individual TL sections, all the TL sections are connected based on a segmentation method, which is a matrix calculation method. The segmentation method accelerates the calculation speed for the PDN impedance estimation. The proposed models are successfully validated by simulations and measurements in the frequency range 0.1-20 GHz. Using the proposed models, we estimate and analyze the impedance curves of the interposer PDN and TSV-based stacked grid-type PDN with respect to the variations in the horizontal area of the interposer PDN and the number of power/ground TSVs in TSV-based stacked grid-type PDNs, respectively.Index Terms-Conformal mapping method, interposer power distribution network (PDN), phenomenological loss equivalence method (PEM), segmentation method, through silicon via (TSV)based stacked grid-type PDN.

Segmentation method based modeling and analysis of a glass package power distribution network (PDN)

“…The segmentation method, which is based on a z-parameter matrix calculation, is a well-known method for the impedance estimation of a whole PDN using a single or multiple unit cells [16][17][18]. Applying the segmentation method to the unit cell shown in Fig.…”

“…For silicon package PDN, due to process limitation associated with CMOS design rules, PDN must be designed in form of mesh or grid. In such case, even unit cell should be divided into multiple sections [17,18]. However, power and ground metal planes can be fabricated in the glass package and as a result, PDN of the whole glass package can be modeled by single unit cell similar to organic package [19].…”

Impedance modeling and analysis of multi-stacked on-chip power distribution network in 3D ICs

“…It leads to the inaccurate partial TSV inductances in a real multiply stacked PDN which has an uneven power distribution. In [16,17], it uses a segmentation method to model the PDNs with multiply pairs of P/G TSVs. It considers the effects of P/G TSV pairs to estimate the impedance of the 3D stacked PDN.…”