Thin‐film transistors (TFTs) based on amorphous indium‐gallium‐zinc‐oxide (a‐IGZO) have attracted vast attention for use in organic light‐emitting diode (AMOLED) displays due to their high electron mobility and large current on–off ratio. Although amorphous oxide semiconductors show considerably less threshold voltage (Vth) variation than poly‐silicon, large‐area processing and degradation effects can impede the characteristic parameters of a‐IGZO TFTs, which manifests in an uneven brightness distribution across the display panel. Such Vth variations are usually reduced by additional compensation circuits consisting of TFTs and capacitors. Herein, a new approach to compensate such variabilities is demonstrated: the integration of a programmable ferroelectric (FE) film in the gate stack of the TFT. This simplifies the complexity of the pixel cell and potentially minimizes the need for compensation circuits, which is crucial for transparent displays. To test this new approach, fully integrated FE‐TFTs (i.e., with vias contacting a structured bottom gate electrode from the top) based on a‐IGZO and FE hafnium‐zirconium oxide (HZO) are developed. A single low‐temperature post‐fabrication treatment at 350 °C for 1 h in air is used to simultaneously crystallize the HZO film in the FE phase and to reduce the number of defects in the a‐IGZO channel. The structural and electrical characterizations provide comprehensive guidance for the design of effective FE‐TFT gate stacks and device geometries. An accurate control of the polarization state and linear switching between multiple intermediate states is shown by using programming pulses of various amplitudes and widths. Furthermore, a direct correlation between the channel length and the applied pulse width for programming is observed.

To investigate the process temperature on the growth of ultra-thin (≤ 500 nm) Cu(In,Ga)Se 2 (CIGSe) absorbers and the corresponding performance of solar cells, the process temperature was set to 610 °C and 440 °C, respectively. It was found that the low process temperature (440 °C) could reduce the inter-diffusion of GaIn and thus result in a higher back [Ga]/([Ga]+[In]) ([Ga]/[III]) grading than at the temperature of 610 °C. The higher back [Ga]/[III] grading at 440 °C was evidenced to both electrically and optically contribute to the efficiency enhancement of the solar cells in contrast to the lower back [Ga]/[III] grading at 610 °C. It was also implied that the high back [Ga]/[III] grading was beneficial to the collection of carriers generated from the back-reflected light.

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The article demonstrates how quantitative compositional depth profiles of Cu(In,Ga)(S,Se)2 layers can be utilized to determine their energy bandgap distribution.