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Nano-sheets are the revolutionary change to overcome the limitations of FinFET. In this paper, the temperature dependence of 10 nm junctionless (JL) nano-sheet FET performance on DC, analog and RF characteristics are investigated for the first time using extended source/drain and with high-k gate stack. The detailed DC performance analysis like transfer characteristics (ID-VGS), output characteristics (ID-VDS), DIBL, SS and ION/IOFF ratio are evaluated from 200 K to 350 K. We also analyzed the temperature effect on the ON-OFF performance metric (Q), dynamic power, and power consumption. Furthermore, to understand the device performance on various process parameters like doping, and work function variations are presented at 300 K. The proposed device exhibits good ION/IOFF switching behaviour with IOFF reaching less than nA for all temperatures. The cut-off frequency (ft) is determined to be in the THz range and the ON-OFF performance metric (Q) ranges between 1.5 to 2.2 μS-dec/mV at LG of 10 nm. Furthermore, the scaling effect of nano-sheet at various gate lengths (LG = 5 nm, 8 nm, 10 nm, 14 nm, and 20 nm) are also presented. From simulation analysis we notice that analog/RF performance parameters of a JL nano-sheet FET are less sensitive to temperature variations. At extremely scaled LG the nano-sheet FET exhibits lower power consumption and dynamic power and comparatively decreases with increase in temperature. The proposed nano-sheet FET demonstrates as a strong potential contender for low-power and high-frequency applications at nano-regime.

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Silicon (Si) nanosheet (NS) metal-oxide semiconductor field effect transistors (MOSFETs) are realized as an outstanding structure to obtain better area scaling and power performance compared to FinFETs. The Si NS MOSFETs provide high current drivability due to wider effective channel (W eff) and maintain better short channel performance. Here, the performance of junctionless (JL) SOI NS p-MOSFET is evaluated by invoking HfxTi1−xO2 gate stack to overcome adverse short channel effects (SCEs). The device performance is enhanced using various spacer dielectrics and the electrical characteristics are presented. Moreover, the effect of NS width variation on I ON/I OFF, SS, V th is presented and the analog/RF metrics of the device are evaluated. The power consumption, dynamic power, and static power analyses of NS MOSFET is presented with respect to the ITRS road map. Our investigation reveals that the device exhibits an I ON/I OFF ratio of more than ∼106 with NS widths of 10 to 30 nm, respectively. The device exhibits better performance (I ON) with higher NS widths and ensures potential towards high-performance applications. However, with an increase in NS widths the threshold voltage (V th) tends to downfall and leads to deterioration in subthreshold performance . With high-k spacer dielectric the device exhibits better static power consumption for the CMOS inverter. By careful control of NS width and effective usage of spacer dielectric ensures better p-MOSFET design for future technology nodes.