p-Type Trigate Junctionless Nanosheet MOSFET: Analog/RF, Linearity, and Circuit Analysis

Sreenivasulu, V. Bharath; Narendar, Vadthiya

doi:10.1149/2162-8777/ac3bdf

Cited by 20 publications

(9 citation statements)

References 43 publications

(52 reference statements)

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“…Also, as the NS H is raised from 5 nm to 9 nm, a fall of 12.7% and 17.3% for NS W of 10 nm and 50 nm is noticed. Figure 8c depicts the transconductance frequency product (TFP) and is essential analog/ RF FOM, 23 which is the product of g m and f T . The TFP is used in high and medium speed circuit applications to provide a trade-off between the power and bandwidth.…”

Section: Figure 8b Depicts the Delay τmentioning

confidence: 99%

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Common Source Amplifier and Ring Oscillator Circuit Performance Optimization Using Multi-Bridge Channel FETs

Sreenivasulu

Neelam

Vakkalakula

et al. 2023

ECS J. Solid State Sci. Technol.

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Direct current, analog/radio frequency device, and circuit applications of nanosheet (NS) field effect transistors were investigated. To enhance power performance, co-optimization geometry parameters like NS width (NSW) and NS thickness (NSH) are varied for high-performance and low-power applications. A rise of 1.47x in ION and a rise of 5.8x in IOFF is noticed with an increase in NSH due to enlarged effective width (Weff). In addition, a rise of 3.8x in ION and a fall of 76.4% in IOFF is noticed with higher NSW. Larger NSW ensures better transconductance, transconductance generation factor, cut-off frequency, gain-band width product, transconductance frequency product, and intrinsic delay. The optimized supply voltage for maximum voltage gain of common source amplifier and three stage ring oscillators (RO) with varied NSW was performed. The impact of number of stages (N) of three stage RO for better frequency of oscillations was studied for high-frequency circuit applications.

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Section: Figure 8b Depicts the Delay τmentioning

confidence: 99%

“…The gain bandwidth product (GBW) is used to estimate the device efficacy in high frequency applications. 23 Mathematically GBW can be evaluated as: 26 GBW g C 20 6…”

Section: Figure 8b Depicts the Delay τmentioning

confidence: 99%

Common Source Amplifier and Ring Oscillator Circuit Performance Optimization Using Multi-Bridge Channel FETs

Sreenivasulu

Neelam

Vakkalakula

et al. 2023

ECS J. Solid State Sci. Technol.

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“…The maximum output power density. P out of 23 dBm and the maximum PAE of 63.3% are achieved at 3.12 GHz with V ds = 10 V. Input and output matching networks are essential to reduce reflections; minimise NF min ; maximise the power transfer, linearity, and bandwidth; and to achieve unconditional stability 18,41–45 …”

Section: Noise Modelling In Vertical Cavet Gan Mis‐hemtsmentioning

confidence: 99%

Noise characterisation of GaN current aperture vertical electron transistor metal‐insulated semiconductor field effect transistor with Δ‐shaped gate for low noise radio frequency amplifiers

Janakiraman

Mohanbabu

Maheswari

et al. 2022

Int J RF Mic Comp-Aid Eng

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In this article, vertical CAVET with boron-doped GaN layer as current blocking layer (CBL) for AlGaN/GaN is proposed in this study, and different electrical characteristics of the devices, such as DC (I ds À V ds ), small-signal radio frequency and high-frequency microwave noise performances, are characterised using Synopsys TCAD simulations. The vertical CAVET AlGaN/GaN metal-insulated semiconductor field effect transistor (MIS-HEMT) has been found to have a high threshold V T = 6.36 V, drain saturation current, I ds,sat = 3.41 kA/cm 2 , reduced OFF-state current <10 À12 and improved high frequency and noise performances. The findings provide insight on noise sources and provide information on how to improve GaN transistor noise performance. Its useful characterisation tool for learning more about the imperfections in advanced AlGaN/GaN MIS-HEMTs and how they evolve. A twoport noise equivalent-circuit description is used to calculate data for noise.Using data from noise and scattering parameters that have been measured, we evaluated the effect of noise sources due to gate and drain, as well as their correlation. The devices exhibit a minimum noise figure (NF min ) and an equivalent noise resistance (R n ) of 1.21 dB and 20 Ω at 20 GHz, with V gs = 5 V and V ds = 10 V, which is small and appropriate for low-noise amplifiers with a wide bandwidth. The maximum output power density P out of 23 dBm and the maximum PAE of 63.3% are achieved for GaN V-shaped CAVET MIS-HEMTs with V ds = 10 V at 3.12 GHz is achieved. A comparison is made between the noise performance of conventional HEMTs, MIS-HEMTs and FETs. The methods for obtaining the noise figure (NF min ) and other noise metrics are then explained and compared with those found in the literature.

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“…9,10 Researchers came up with the implementation of high-k gate stack to combat this problem. 11 Also, multiple device engineering such as Silicon on Insulator (SOI) technology, 12 2D channel materials, 13 Double gate (DG), 14 Trigate, 15 Fin-shaped field effect transistor (FinFET), 16 gate all around (GAA) FETs [17][18][19][20] are implemented. In the DG transistor, the gate is present at the top and down sides of the channel and improves the gate's electrostatic integrity and offers better short channel performance.…”

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confidence: 99%

Impact of Scaling on Nanosheet FET and CMOS Circuit Applications

Neelam

Sreenivasulu

Pothupogu

2023

ECS J. Solid State Sci. Technol.

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The impact of scaling on the gate all around the nanosheet field effect transistor (NSFET) was studied in detail at sub-5-nm nodes for digital and analog/RF applications. When LG is scaled from 20 to 5 nm, ION is improved by 2.1×, IOFF increases by three orders of magnitude, SS increases by 27%, DIBL is increased by 4×, and a Vth roll off of 41 mV is noticed. Further, an enhancement of 3.65× was noticed in cut-off frequency (fT) with scaling of LG from 20 to 5 nm. The complimentary metal oxide semiconductor (CMOS) inverter and ring oscillator’s performance was studied in detail with LG scaling. With LG scaling from 20 to 5 nm, the inverter performance metrics like switching current is increased by 3.87×, propagation delay (τP), energy delay product and power delay product are reduced by 65%, 5.5× and 1.95×, respectively. Moreover, the ring oscillator offers superior performance with an oscillation frequency of 98.05 GHz when LG is scaled to 5nm, which is 157% more than fOSC at LG of 20 nm. Thus the analyses reveal the scaling capability of NSFET at both device and circuit levels for sub-5-nm nodes.

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p-Type Trigate Junctionless Nanosheet MOSFET: Analog/RF, Linearity, and Circuit Analysis

Cited by 20 publications

References 43 publications

Common Source Amplifier and Ring Oscillator Circuit Performance Optimization Using Multi-Bridge Channel FETs

Common Source Amplifier and Ring Oscillator Circuit Performance Optimization Using Multi-Bridge Channel FETs

Noise characterisation of GaN current aperture vertical electron transistor metal‐insulated semiconductor field effect transistor with Δ‐shaped gate for low noise radio frequency amplifiers

Impact of Scaling on Nanosheet FET and CMOS Circuit Applications

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