Analytical modeling and simulation of multigate FinFET devices and the impact of high-k dielectrics on short channel effects (SCEs)

Narendar, Vadthiya; Mishra, R. A.

doi:10.1016/j.spmi.2015.06.004

Cited by 99 publications

(39 citation statements)

References 39 publications

(31 reference statements)

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“…The critical electrical parameters such as SS (subthreshold swing) and DIBL (drain-induced barrier lowering) are defined below [4]: (4) (5) Fig. 1.…”

Section: Device Simulation Using Silvaco-atlasmentioning

confidence: 99%

“…The gate voltage V GS was swept from 0 to 1 V with a step of 0.02 V. The threshold voltage and maximum transconductance were 0.27 V and 29.54 μA/V at V DS = 0.1 V, respectively, as illustrated in Fig. 2(a) [17,18].…”

Section: Device Simulation Using Silvaco-atlasmentioning

confidence: 99%

“…For FinFET, the body thickness T Fin should be approximately half of the gate length L G to provide better control of short channel effects. When the L G /T FIN ratio is smaller than 1.5, the drain induced barrier lowering, subthreshold swing, and leakage current are increased sensibly [2][3][4][5][6][7][8].…”

Section: Introductionmentioning

confidence: 99%

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Temperature Dependence of Electrical Parameters of Silicon-on-Insulator Triple Gate n-Channel Fin Field Effect Transistor

Boukortt¹,

Hadri²,

Caddemi³

et al. 2016

Transactions on Electrical and Electronic Materials

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In this work, the temperature dependence of electrical parameters of nanoscale SOI (silicon-on-insulator) TG (triple gate) n-FinFET (n-channel Fin field effect transistor) was investigated. Numerical device simulator ATLAS™ was used to construct, examine, and simulate the structure in three dimensions with different models. The drain current, transconductance, threshold voltage, subthreshold swing, leakage current, drain induced barrier lowering, and on/ off current ratio were studied in various biasing configurations. The temperature dependence of the main electrical parameters of a SOI TG n-FinFET was analyzed and discussed. Increased temperature led to degraded performance of some basic parameters such as subthreshold swing, transconductance, on-current, and leakage current. These results might be useful for further development of devises to strongly down-scale the manufacturing process.

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“…The critical electrical parameters such as SS (subthreshold swing) and DIBL (drain-induced barrier lowering) are defined below [4]: (4) (5) Fig. 1.…”

Section: Device Simulation Using Silvaco-atlasmentioning

confidence: 99%

Section: Device Simulation Using Silvaco-atlasmentioning

confidence: 99%

See 1 more Smart Citation

Temperature Dependence of Electrical Parameters of Silicon-on-Insulator Triple Gate n-Channel Fin Field Effect Transistor

Boukortt¹,

Hadri²,

Caddemi³

et al. 2016

Transactions on Electrical and Electronic Materials

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show abstract

“…The study of the advanced FinFET technology is a current topic of research for all the production companies, like TSMC, Intel, and Samsung, which are in the race to get a high performance of microprocessors beyond the barrier of 14 nm. Among all, FinFET is one of the most attractive devices for implementing nanoscale CMOS technology node applications, since this type of transistor provides a better scalability option due to its excellent immunity to short channel effects (SCEs) [1][2][3][4][5][6]. For the FinFET, the body thickness (T Fin ) should be approximately half of the gate length (L G ) to provide better control of short channel effects (SCEs).…”

Section: Introductionmentioning

confidence: 99%

“…For the FinFET, the body thickness (T Fin ) should be approximately half of the gate length (L G ) to provide better control of short channel effects (SCEs). The drain induced barrier lowering (DIBL), subthreshold slope (SS), and leakage current (I off ) increase sensibly when L G /T Fin ratio is smaller than 1.5 [2,7]. The use of silicon on insulator substrate for manufacturing microprocessors was introduced from the major semiconductor companies with the aim to minimize parasitic capacitances and to improve current drive, circuit speed, and power consumption [1].…”

Section: Introductionmentioning

confidence: 99%

Simulation of a Nanoscale SOI TG n-FinFET

Boukortt¹,

Hadri²,

Caddemi³

2016

IJCA

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The objective of this work is to study the electrical characteristics of a nanoscale SOI Tri-Gate n-channel fin field-effect transistor (FinFET) structure with 8 nm gate length using Semiconductor TCAD tools. ATLAS™ tools are computer programs which allow for the creation, fabrication, and simulation of semiconductor devices in three dimensions with different models under consideration. The drain current, transconductance, threshold voltage, subthreshold slope, leakage current, drain induced barrier lowering, and I On /I Off current ratio are analyzed in the various biasing configuration. In addition, FinFET device with a high value of gate dielectric constant exhibits much better performance compared to the Si 3 N 4 dielectric material, which is desirable for high performance low-power/low-voltage applications. It is found that increasing the high-k value was beneficial in reducing the subthreshold slope, DIBL, and leakage current. General TermsIntegrated Circuit, VLSI, FinFET Device Modeling.

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Design insights into RF /analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications

Sreenivasulu

Narendar

2021

Int J RF Mic Comp-Aid Eng

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Multi-fin devices are the most reliable option for terahertz (THz) frequency applications at nano-regime. In this work impact of spacer engineering on multi-fin SOI FET performance is evaluated by invoking single low-k (Air), high-k (Si 3 N 4 , HfO 2 ), and hybrid dual-k (Air + Si 3 N 4 ) spacer in the underlap section at nano-regime. The simulation study reveals that the high-k (HfO 2 ) spacer gives a higher switching ratio (I ON /I OFF ) in the order of ~10 7 , subthreshold swing (SS) = 72 mV/dec, drain induced barrier lowering (DIBL) = 22.14 mV/V and quality factor (Q) = g m /SS = 0.16 μS-dec/mV. Furthermore, to measure the suitability of the device for high frequency applications various analog/RF parameters are studied. The high-k (HfO 2 ) spacer dominates DC and analog performance, whereas the low-k (Air) spacer dominates the RF domain with f T = 1.26 THz, GBW = 0.251 THz, TFP = 29 THz range, and with smaller intrinsic delays. Hybrid dual-k spacer (Air + Si 3 N 4 ) outperforms in terms of gain (A V ) and output resistance (R o ). The Air spacer exhibits lower dynamic power of 2.09 aJ/μm and power consumption of 1.04 aJ/μm. The linearity metrics for multi-fin SOI FET parameters like g m2 , g m3 , HD1, HD2, THD, and VIP2 are also studied. The Air spacer followed by hybrid spacer outperforms in linearity, and harmonic distortion components and ensures its potential for RF applications at nano-regime.

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Analytical modeling and simulation of multigate FinFET devices and the impact of high-k dielectrics on short channel effects (SCEs)

Cited by 99 publications

References 39 publications

Temperature Dependence of Electrical Parameters of Silicon-on-Insulator Triple Gate n-Channel Fin Field Effect Transistor

Temperature Dependence of Electrical Parameters of Silicon-on-Insulator Triple Gate n-Channel Fin Field Effect Transistor

Simulation of a Nanoscale SOI TG n-FinFET

Design insights into RF /analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications

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