Simulation of a Nanoscale SOI TG n-FinFET

Abstract

The objective of this work is to study the electrical characteristics of a nanoscale SOI Tri-Gate n-channel fin field-effect transistor (FinFET) structure with 8 nm gate length using Semiconductor TCAD tools. ATLAS™ tools are computer programs which allow for the creation, fabrication, and simulation of semiconductor devices in three dimensions with different models under consideration. The drain current, transconductance, threshold voltage, subthreshold slope, leakage current, drain induced barrier lowering, and I On /I Off current ratio are analyzed in the various biasing configuration. In addition, FinFET device with a high value of gate dielectric constant exhibits much better performance compared to the Si 3 N 4 dielectric material, which is desirable for high performance low-power/low-voltage applications. It is found that increasing the high-k value was beneficial in reducing the subthreshold slope, DIBL, and leakage current. General TermsIntegrated Circuit, VLSI, FinFET Device Modeling.

Temperature Dependence of Electrical Parameters of Silicon-on-Insulator Triple Gate n-Channel Fin Field Effect Transistor

“…Therefore, high-k dielectric materials (Al 2 O 3 , La 2 O 3 , and ZrO 2 ) are considered as promising solution to improve gate control on the channel region and increase electrical performance [11]. The region between the source and the drain of the considered device is covered by zirconium dioxide (ZrO 2 , κ = 25) as high-κ gate dielectric materials to allow further miniaturization of electronic components [12,13].…”