Design insights into RF /analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications

Abstract

Multi-fin devices are the most reliable option for terahertz (THz) frequency applications at nano-regime. In this work impact of spacer engineering on multi-fin SOI FET performance is evaluated by invoking single low-k (Air), high-k (Si 3 N 4 , HfO 2 ), and hybrid dual-k (Air + Si 3 N 4 ) spacer in the underlap section at nano-regime. The simulation study reveals that the high-k (HfO 2 ) spacer gives a higher switching ratio (I ON /I OFF ) in the order of ~10 7 , subthreshold swing (SS) = 72 mV/dec, drain induced barrier lowering (DIBL) = 22.14 mV/V and quality factor (Q) = g m /SS = 0.16 μS-dec/mV. Furthermore, to measure the suitability of the device for high frequency applications various analog/RF parameters are studied. The high-k (HfO 2 ) spacer dominates DC and analog performance, whereas the low-k (Air) spacer dominates the RF domain with f T = 1.26 THz, GBW = 0.251 THz, TFP = 29 THz range, and with smaller intrinsic delays. Hybrid dual-k spacer (Air + Si 3 N 4 ) outperforms in terms of gain (A V ) and output resistance (R o ). The Air spacer exhibits lower dynamic power of 2.09 aJ/μm and power consumption of 1.04 aJ/μm. The linearity metrics for multi-fin SOI FET parameters like g m2 , g m3 , HD1, HD2, THD, and VIP2 are also studied. The Air spacer followed by hybrid spacer outperforms in linearity, and harmonic distortion components and ensures its potential for RF applications at nano-regime.

Investigation of variation in temperature on steep subthreshold slope nanowire tunnel field effect transistor based biosensor

“…The idea behind it is that the device nonlinearity can be modeled using a lower-order polynomial which can be derived by using Taylor series expansion. IMD 3 is more for higher values of temperature and is also more for higher dielectric constant [34]. IMD 3 if highest for k = 25 at T=400 K and lowest for k = 3 at T=200 K is shown in figures 11(a) and (b).…”

Investigation of spacer-engineered stacked nanosheet tunnel FET with varying design attributes

“…Higher TGF makes HfO 2 a better candidate for analogue applications. The total gate capacitance (C GG ) refers to the combined capacitance between the gate and the source (C GS ) and drain (C GD ) terminals [34]. The capacitances C GS and C GD encompass additional parasitic capacitances, such as the outer fringing capacitance (C OF ), inner source fringing capacitance (C SIF ), and inner drain fringing capacitance (C DIF ).…”

“…The capacitances C GS and C GD encompass additional parasitic capacitances, such as the outer fringing capacitance (C OF ), inner source fringing capacitance (C SIF ), and inner drain fringing capacitance (C DIF ). C OF , C SIF , and C DIF rise as dielectric permittivity increases [34]. Figure 7 depicts the relationship between total gate capacitance (C GG ) and V GS with varying dielectric permittivity.…”

Nanosheet Field Effect Transistor Device and Circuit Aspects for Future Technology Nodes

“…For efficient VLSI architectures 13,14 are proposed to improve the device's performance, such as Negative Capacitance FET (NCFET) design models to provide a steeper switching slope. 15 To replace the traditional MOSFET's multi-gate structures is proposed to improve the gate controllability and diminish SCEs. Advancements made to conventional MOSFET are done by adding another gate, named Double Gate MOSFET.…”