2021
DOI: 10.1007/s12633-021-01145-w
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Design and Temperature Assessment of Junctionless Nanosheet FET for Nanoscale Applications

Abstract: Nano-sheets are the revolutionary change to overcome the limitations of FinFET. In this paper, the temperature dependence of 10 nm junctionless (JL) nano-sheet FET performance on DC, analog and RF characteristics are investigated for the first time using extended source/drain and with high-k gate stack. The detailed DC performance analysis like transfer characteristics (ID-VGS), output characteristics (ID-VDS), DIBL, SS and ION/IOFF ratio are evaluated from 200 K to 350 K. We also analyzed the temperature effe… Show more

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Cited by 40 publications
(18 citation statements)
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“…These leakages will increase the off current of the device. Moreover, the increment in off current is observed for higher thickness values of nanosheet because of reduction in potential barrier height, conduction band energy in the channel for off state condition [31].…”
Section: Impact On DC Performance Of Nsfet With Geometric Variationsmentioning
confidence: 96%
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“…These leakages will increase the off current of the device. Moreover, the increment in off current is observed for higher thickness values of nanosheet because of reduction in potential barrier height, conduction band energy in the channel for off state condition [31].…”
Section: Impact On DC Performance Of Nsfet With Geometric Variationsmentioning
confidence: 96%
“…To ensure better electrostatic integrity, the EOT of 0.78 nm and gate work function of 4.6 eV are taken for all simulations. To improve the subthreshold behaviour, a nitride spacer with a length of 5 nm is maintained throughout the simulations [31].…”
Section: Nsfet Structure and Simulation Proceduresmentioning
confidence: 99%
“…9. The process ow is similar to the modern fabrication style [33], [34]. Wafer selection plays an important role for design of wearable antenna, it mainly effects the antenna parameters.…”
Section: G Fabrication Ow Of Silicon Wearable Body Area Antennamentioning
confidence: 99%
“…Increasing the number of fins between source and drain with limited heights, multi-fin FETs strive to have a higher current drive and power gain capabilities. 15,16 To further increase the performance and control over SCEs, spacers are invoked for the underlap, which increases the distance between two potential terminals thereby reducing the effect of the drain potential on the channel, which may lead to channel length modulation. The introduction of underlap spacers suppresses the parasitic capacitance formed by abrupt junctions.…”
Section: Introductionmentioning
confidence: 99%