Design and Temperature Assessment of Junctionless Nanosheet FET for Nanoscale Applications

Sreenivasulu, V. Bharath; Narendar, Vadthiya

doi:10.1007/s12633-021-01145-w

Cited by 40 publications

(18 citation statements)

References 31 publications

(18 reference statements)

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“…These leakages will increase the off current of the device. Moreover, the increment in off current is observed for higher thickness values of nanosheet because of reduction in potential barrier height, conduction band energy in the channel for off state condition [31].…”

Section: Impact On DC Performance Of Nsfet With Geometric Variationsmentioning

confidence: 96%

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Performance Evaluation of GAA Nanosheet FET with Varied Geometrical and Process Parameters

Neelam

Prithvi

2022

Silicon

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Nanosheet Field Effect Transistor (NSFET) is a viable contender for future scaling in sub-7-nm technology. This paper provides insights into the variations of DC FOMs for different geometrical con gurations of the NSFET. In this script, DC performance of 3D GAA NSFET is analyzed by varying the width, thickness of the device. Moreover, the gate length is scaled from 20 nm to 5 nm to check for the device suitability in logic applications. The thickness and width of each nanosheet are varied in the range of 5 to 9 nm, and 10 to 50 nm respectively to analyse the performance dependency on the geometry of the device. The impact of geometry of NSFET on various DC performance metrics like transfer characteristics, sub-threshold swing (SS), on current (I ON ), off current (I OFF ), switching ratio (I ON /I OFF ), threshold voltage (V th ) and drain induced barrier lowering (DIBL) are studied. On top of that, the device's electrical characteristics are analyzed for a wide range of temperatures from -43 o C to 127 o C to identify the temperature compensation point and is observed at V GS = 0.55 V and I D = 3.86 × 10 −6 A. Furthermore, the important process parameter, work function variations on transfer characteristics of the device is analyzed. Moreover, the analyses tell that, for sub -7 nm, the NSFET is a potential device for high performance and good logic applications.

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Section: Impact On DC Performance Of Nsfet With Geometric Variationsmentioning

confidence: 96%

“…To ensure better electrostatic integrity, the EOT of 0.78 nm and gate work function of 4.6 eV are taken for all simulations. To improve the subthreshold behaviour, a nitride spacer with a length of 5 nm is maintained throughout the simulations [31].…”

Section: Nsfet Structure and Simulation Proceduresmentioning

confidence: 99%

Performance Evaluation of GAA Nanosheet FET with Varied Geometrical and Process Parameters

Neelam

Prithvi

2022

Silicon

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“…9. The process ow is similar to the modern fabrication style [33], [34]. Wafer selection plays an important role for design of wearable antenna, it mainly effects the antenna parameters.…”

Section: G Fabrication Ow Of Silicon Wearable Body Area Antennamentioning

confidence: 99%

Silicon Wearable Body Area Antenna for Speech Enhanced IOT and Medical Applications

Vignesh

Kanithan

Jana

et al. 2021

Preprint

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We propose in this paper a reduction in the size of wearable antennas on silicon (Si) for medicinal frameworks and Internet of things (IoT). This research also introduces one more type of dynamic patch antenna designed in favor of speech-enhanced healthcare applications. The most significant impediment to the adoption of smart correspondence and medical services frameworks is voice-enabled IoT. The primary objective of a body area network (BAN) is to give ceaselessly clinical information to the doctors. Actually wireless body area network is flexible, dense, trivial and less expensive. On the other hand the main disadvantage is low efficiency for small printed antenna. Microstrip silicon antenna recurrence is changed because of ecological conditions, distinctive reception apparatus areas and diverse framework activity modes. By using tunable antenna the efficiency of bandwidth usage can be increased. Amplifiers are associated with the feed line of antenna in order to build its dynamic range. In this study, a dynamic polarized antenna is constructed, analysed and attempted for fabrication. The gain of the antenna is 13 ± 2dB for the frequency range of 390 to 610MHz. The output of the polarized antenna is roughly 19 dBm. At different environmental conditions the performance and ability to control the antenna could vary. To achieve stable performance, we have used varactor diode and voltage controlled diode. This silicon wearable antenna can be fabricated and tested for many medical applications like health monitoring system, pacemakers etc. Furthermore, Micromachining techniques can be used to lower the practical dielectric constant of Silicon and hence improve radiation efficiency.

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“…Increasing the number of fins between source and drain with limited heights, multi-fin FETs strive to have a higher current drive and power gain capabilities. 15,16 To further increase the performance and control over SCEs, spacers are invoked for the underlap, which increases the distance between two potential terminals thereby reducing the effect of the drain potential on the channel, which may lead to channel length modulation. The introduction of underlap spacers suppresses the parasitic capacitance formed by abrupt junctions.…”

Section: Introductionmentioning

confidence: 99%

Design insights into RF /analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications

Sreenivasulu

Narendar

2021

Int J RF Mic Comp-Aid Eng

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Multi-fin devices are the most reliable option for terahertz (THz) frequency applications at nano-regime. In this work impact of spacer engineering on multi-fin SOI FET performance is evaluated by invoking single low-k (Air), high-k (Si 3 N 4 , HfO 2 ), and hybrid dual-k (Air + Si 3 N 4 ) spacer in the underlap section at nano-regime. The simulation study reveals that the high-k (HfO 2 ) spacer gives a higher switching ratio (I ON /I OFF ) in the order of ~10 7 , subthreshold swing (SS) = 72 mV/dec, drain induced barrier lowering (DIBL) = 22.14 mV/V and quality factor (Q) = g m /SS = 0.16 μS-dec/mV. Furthermore, to measure the suitability of the device for high frequency applications various analog/RF parameters are studied. The high-k (HfO 2 ) spacer dominates DC and analog performance, whereas the low-k (Air) spacer dominates the RF domain with f T = 1.26 THz, GBW = 0.251 THz, TFP = 29 THz range, and with smaller intrinsic delays. Hybrid dual-k spacer (Air + Si 3 N 4 ) outperforms in terms of gain (A V ) and output resistance (R o ). The Air spacer exhibits lower dynamic power of 2.09 aJ/μm and power consumption of 1.04 aJ/μm. The linearity metrics for multi-fin SOI FET parameters like g m2 , g m3 , HD1, HD2, THD, and VIP2 are also studied. The Air spacer followed by hybrid spacer outperforms in linearity, and harmonic distortion components and ensures its potential for RF applications at nano-regime.

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Design and Temperature Assessment of Junctionless Nanosheet FET for Nanoscale Applications

Cited by 40 publications

References 31 publications

Performance Evaluation of GAA Nanosheet FET with Varied Geometrical and Process Parameters

Performance Evaluation of GAA Nanosheet FET with Varied Geometrical and Process Parameters

Silicon Wearable Body Area Antenna for Speech Enhanced IOT and Medical Applications

Design insights into RF /analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications

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