Abstract-Quantum-dot cellular automata (QCA) has been widely advocated as a new device architecture for nanotechnology. Using QCA, the innovative design of digital systems can be achieved by exploiting the so-called capability of processing-in-wire, i.e., signal manipulation proceeds at the same time as propagation. QCA systems require low power together with the potential for high density and regularity. These features make QCA an attractive technology for manufacturing memories in which the in-wire paradigm can be exploited for storage purposes. This paper proposes a novel parallel memory architecture for QCA implementation. This architecture is based on storing information on a QCA line by changing the direction of signal flow among three clocking zones. Timing of these zones requires two additional clocks to implement a four-step process for reading/writing data to the memory. Its operation has been verified by simulation. It is shown that the requirements for clocking, number of zones, as well as the underlying CMOS circuitry are significantly reduced compared with previous QCA parallel architectures.Index Terms-Emerging technologies, memory architecture, quantum-dot cellular automata (QCA), quantum computing.
Abstract-Quantum-dot Cellular Automata (QCA) has been widely advocated as a new device architecture for nanotechnology. QCA systems require extremely low power, together with the potential for high density and regularity. These features make QCA an attractive technology for manufacturing memories in which the paradigm of memory-in-motion can be fully exploited. This paper proposes a novel serial memory architecture for QCA implementation. This architecture is based on utilizing new building blocks (referred to as tiles) in the storage and input/output circuitry of the memory. The QCA paradigm of memory-in-motion is accomplished using a novel arrangement in the storage loop and timing/clocking; a three-zone memory tile is proposed by which information is moved across a concatenation of tiles by utilizing a two-level clocking mechanism. Clocking zones are shared between memory cells and the length of the QCA line of a clocking zone is independent of the word size. QCA circuits for address decoding and input/output for simplification of the Read/Write operations are discussed in detail. An extensive comparison of the proposed architecture and previous QCA serial memories is pursued in terms of latency, timing, clocking requirements, and hardware complexity.
This paper presents a novel memory architecture for implementation by Quantum-dot Cellular Automata (QCA). The proposed architecture combines the advantages of reduced area of a serial memory with the reduced latency in the read operation of a parallel memory. An extensive evaluation with respect to latency and area is pursued. For area analysis, a novel characterization which considers cells in the logic circuitry, interconnect as well as the unused portion of the Cartesian place as QCA layout, is proposed. 1 Summary and conclusions Our proposed novel memory architecture for QCA implementation utilizes a parallel read operation on multiple bit loops. The memory arrangement is referred to as "hy-brid" due to the different operational mechanism for the two memory operations (read and write). The proposed memory results in two advantages over previous architectures: (1) the parallel read mechanism allows a reduced latency compared with O(N) latency for serial memories (where N is the number of bits in a loop.); (2) a reduced area is needed compared with a parallel memory, thus increasing the density of the memory (this is accomplished due to sharing of interconnects, the reduced control logic and a different loop implementation). The hybrid memory is best suited in application in which the memory is often read and seldom written. A novel figure of merit referred to as effective area is introduced in the analysis. The effective area is the geometric area of the memory layout which includes the area of the cells for the logic and interconnect circuits as well as the unused portion of the Cartesian plane (to avoid unwanted Coulombic interactions among cells). Different layouts of the hybrid memory are evaluated using this new metric. 2 Proposed memory architecture The proposed memory architecture can be considered as an evolution of the serial memory presented in [1]. A block diagram of the proposed memory architecture is shown in Figure 2. In this Figure, m loops of 2 n = N bits are arranged to form a m bit word of 2 n = N locations which can be accessed in parallel. Each loop has as inputs the n bit address of the accessed bit and the following additional signals: (1) the R/W# control signal which specifies if the loop is accessed in a write or read operation; (2) the serial data input D in ; (3) a VALID control signal. The last signal is provided to each loop by the adder and allows the synchronization of the write operation. The write operation must be performed serially on the loops and thus, the correct bit must be addressed. For both the read and write operations , addressing the same bit independently of the configuration of the shift register requires the input address to be added to an offset (which is stored in a 2 n counter). The operation of the hybrid memory can be described as follows: when a write is requested, this operation is performed provided the value of the "biased" address ADDR' is zero. When the NOR operation of the bits of the address is equal to one, then the write operation can have at mos...
Quantum-dot Cellular Automata (QCA) has been widely advocated as a new device architecture for nano technology. QCA systems require extremely low power together with the potential for high density and regularity. These features make QCA an attractive technology for manufacturing memories in which the paradigm of memory-in-motion can be fully exploited. This paper proposes a novel serial memory architecture for QCA implementation. This architecture is based on utilizing new building blocks (referred to as tiles) in the storage and input/output circuitry of the memory. The QCA paradigm of memory-in-motion is accomplished using a novel arrangement in the storage loop and timing/clocking; a three-zone memory tile is proposed by which information is moved across a concatenation of tiles by utilizing a two-level clocking mechanism. Clocking zones are shared between memory cells and the length of the QCA line in a clocking zone is independent of word size. This results in a substantial reduction in clocking zones compared with previous serial memories.
This paper presents a novel memory architecture for implementation by Quantum-dot Cellular Automata (QCA) Summary and conclusionsOur proposed novel memory architecture for QCA implementation utilizes a parallel read operation on multiple bit loops. The memory arrangement is referred to as "hybrid" due to the different operational mechanism for the two memory operations (read and write). The proposed memory results in two advantages over previous architectures: (1) the parallel read mechanism allows a reduced latency compared with O(N ) latency for serial memories (where N is the number of bits in a loop.); (2) a reduced area is needed compared with a parallel memory, thus increasing the density of the memory (this is accomplished due to sharing of interconnects, the reduced control logic and a different loop implementation). The hybrid memory is best suited in application in which the memory is often read and seldom written. A novel figure of merit referred to as effective area is introduced in the analysis. The effective area is the geometric area of the memory layout which includes the area of the cells for the logic and interconnect circuits as well as the unused portion of the Cartesian plane (to avoid unwanted Coulombic interactions among cells). Different layouts of the hybrid memory are evaluated using this new metric. Proposed memory architectureThe proposed memory architecture can be considered as an evolution of the serial memory presented in [1].A block diagram of the proposed memory architecture is shown in Figure 2. In this Figure, m loops of 2 n = N bits are arranged to form a m bit word of 2 n = N locations which can be accessed in parallel. Each loop has as inputs the n bit address of the accessed bit and the following additional signals: (1) the R/W# control signal which specifies if the loop is accessed in a write or read operation; (2) the serial data input D in ; (3) a VALID control signal. The last signal is provided to each loop by the adder and allows the synchronization of the write operation. The write operation must be performed serially on the loops and thus, the correct bit must be addressed. For both the read and write operations, addressing the same bit independently of the configuration of the shift register requires the input address to be added to an offset (which is stored in a 2 n counter). The operation of the hybrid memory can be described as follows: when a write is requested, this operation is performed provided the value of the "biased" address ADDR' is zero. When the NOR operation of the bits of the address is equal to one, then the write operation can have at most (2 n − 1) clock cycles delay. If a read must be performed, the value of ADD' is directly provided to the 2 n -to-1 demultiplexers of every loop, thus incurring into an immediate (virtually zero delay) read operation for the addressed m bits word. The logic structure inside each loop is shown in Figure 1. The inputs of the loops are the m bits ADDR', D in , VALID and the R/W# signals, while the output i...
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
hi@scite.ai
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.