QCA memory with parallel read∕serial write: design and analysis

Abstract

This paper presents a novel memory architecture for implementation by Quantum-dot Cellular Automata (QCA) Summary and conclusionsOur proposed novel memory architecture for QCA implementation utilizes a parallel read operation on multiple bit loops. The memory arrangement is referred to as "hybrid" due to the different operational mechanism for the two memory operations (read and write). The proposed memory results in two advantages over previous architectures: (1) the parallel read mechanism allows a reduced latency compared with O(N ) latency for serial memories (where N is the number of bits in a loop.); (2) a reduced area is needed compared with a parallel memory, thus increasing the density of the memory (this is accomplished due to sharing of interconnects, the reduced control logic and a different loop implementation). The hybrid memory is best suited in application in which the memory is often read and seldom written. A novel figure of merit referred to as effective area is introduced in the analysis. The effective area is the geometric area of the memory layout which includes the area of the cells for the logic and interconnect circuits as well as the unused portion of the Cartesian plane (to avoid unwanted Coulombic interactions among cells). Different layouts of the hybrid memory are evaluated using this new metric. Proposed memory architectureThe proposed memory architecture can be considered as an evolution of the serial memory presented in [1].A block diagram of the proposed memory architecture is shown in Figure 2. In this Figure, m loops of 2 n = N bits are arranged to form a m bit word of 2 n = N locations which can be accessed in parallel. Each loop has as inputs the n bit address of the accessed bit and the following additional signals: (1) the R/W# control signal which specifies if the loop is accessed in a write or read operation; (2) the serial data input D in ; (3) a VALID control signal. The last signal is provided to each loop by the adder and allows the synchronization of the write operation. The write operation must be performed serially on the loops and thus, the correct bit must be addressed. For both the read and write operations, addressing the same bit independently of the configuration of the shift register requires the input address to be added to an offset (which is stored in a 2 n counter). The operation of the hybrid memory can be described as follows: when a write is requested, this operation is performed provided the value of the "biased" address ADDR' is zero. When the NOR operation of the bits of the address is equal to one, then the write operation can have at most (2 n − 1) clock cycles delay. If a read must be performed, the value of ADD' is directly provided to the 2 n -to-1 demultiplexers of every loop, thus incurring into an immediate (virtually zero delay) read operation for the addressed m bits word. The logic structure inside each loop is shown in Figure 1. The inputs of the loops are the m bits ADDR', D in , VALID and the R/W# signals, while the output i...

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