Tile-based design of a serial memory in QCA

Abstract

Quantum-dot Cellular Automata (QCA) has been widely advocated as a new device architecture for nano technology. QCA systems require extremely low power together with the potential for high density and regularity. These features make QCA an attractive technology for manufacturing memories in which the paradigm of memory-in-motion can be fully exploited. This paper proposes a novel serial memory architecture for QCA implementation. This architecture is based on utilizing new building blocks (referred to as tiles) in the storage and input/output circuitry of the memory. The QCA paradigm of memory-in-motion is accomplished using a novel arrangement in the storage loop and timing/clocking; a three-zone memory tile is proposed by which information is moved across a concatenation of tiles by utilizing a two-level clocking mechanism. Clocking zones are shared between memory cells and the length of the QCA line in a clocking zone is independent of word size. This results in a substantial reduction in clocking zones compared with previous serial memories.

Design and simulation of modular 2n to 1 quantum‐dot cellular automata (QCA) multiplexers

“…According to previous studies, several logic gates and computing devices [13] are implemented with QCA. Basic implementations that have been proposed are the binary wire [6], the majority gate, AND gate [14], OR gate [14], NOT gate [14], XOR gate [14], bit-serial adder [15,16], full adder [1,14,15,17,18], multiplier [19], multiplexer [1,2], flip-flop [20][21][22], serial memory [23,24], parallel memory [25], Arithmetic Logic Unit [1,26], microprocessor [26], Programmable Logic Array (PLA) [27], etc.…”

Novel memory designs for QCA implementation

“…In particular, three zones are defined, each clocked with a different signal to provide the execution of four operational steps, i.e. allowing terminal Z of the MV to operate alternatively as an input or as an output (for details see [12], [11]). The main advantage of the line-based approach is that the clocking distribution circuitry is dramatically simplified because the same clocking zones can be shared by different memory cells as per the following implementations.…”

“…The memory cell of the line based serial architecture [12] consists of two long horizontal wires connected together at both ends by two short vertical wires, thus creating a loop for the memory-in-motion paradigm. Three types of tiles are utilized for a QCA implementation of this architecture, input and output tiles (which close the loop as in typical serial QCA memory implementations) and the internal memory tile, which is based on the dual-way Majority Voter operational principle (as discussed previously).…”

Timing Verification of QCA Memory Architectures

“…Differently from all previous architectures (based on a loop structure), the so-called line based approach exploits the Majority Voter (MV) as a memory element [7]. MV Step 1…”

“…Step 4 The memory cell of a line based serial architecture [7] relies on the bidirectional clocking scheme used for the parallel line based memory. This memory consists of two long horizontal wires connected together at both ends by two short vertical wires (Fig.…”