The aim of this paper is to present a flexible and open-source multi-scale simulation software which has been developed by the Device Modelling Group at the University of Glasgow to study the charge transport in contemporary ultra-scaled Nano-CMOS devices. The name of this new simulation environment is Nano-electronic Simulation Software (NESS). Overall NESS is designed to be flexible, easy to use and extendable. Its main two modules are the structure generator and the numerical solvers module. The structure generator creates the geometry of the devices, defines the materials in each region of the simulation domain and includes eventually sources of statistical variability. The charge transport models and corresponding equations are implemented within the numerical solvers module and solved self-consistently with Poisson equation. Currently, NESS contains a drift–diffusion, Kubo–Greenwood, and non-equilibrium Green’s function (NEGF) solvers. The NEGF solver is the most important transport solver in the current version of NESS. Therefore, this paper is primarily focused on the description of the NEGF methodology and theory. It also provides comparison with the rest of the transport solvers implemented in NESS. The NEGF module in NESS can solve transport problems in the ballistic limit or including electron–phonon scattering. It also contains the Flietner model to compute the band-to-band tunneling current in heterostructures with a direct band gap. Both the structure generator and solvers are linked in NESS to supporting modules such as effective mass extractor and materials database. Simulation results are outputted in text or vtk format in order to be easily visualized and analyzed using 2D and 3D plots. The ultimate goal is for NESS to become open-source, flexible and easy to use TCAD simulation environment which can be used by researchers in both academia and industry and will facilitate collaborative software development.

We investigated the device performance of the optimized 3-nm gate length (L G ) bulk Silicon FinFET device using 3-D quantum transport device simulation. By keeping source and drain doping constant and by varying only the channel doping, the simulated device is made to operate in three different modes such as inversion (IM) mode, accumulation (AC) mode and junctionless (JL) mode. The excellent electrical characteristics of the 3-nm gate length Si-based bulk FinFET device were investigated. The sub threshold slope values (SS~65mV/dec.) and drain-induced barrier lowering (DIBL<17mV/V) are analyzed in all three IM, AC and JL modes bulk FinFET with |V TH | ~0.31 V. Furthermore, the threshold voltage (V TH ) of the bulk FinFET can be easily tuned by varying the work function (WK). This research reveals that Moore's law can continue up to 3-nm nodes.

Silicon (Si) and Germanium (Ge) ultrathin body junctionless field-effect transistor (UTB-JLFET) with L G = 1 nm and L G = 3 nm were demonstrated by solving the coupled drift-diffusion and density-gradient model. The simulation results show that the Si and Ge channel can be used in ultrashort channel device as long as UTB is employed. As UTB is employed, ultrashort channel device does not need to follow an empirical rule of T ch = L G /3. Furthermore, Ge UTB-JLFET 6T-SRAM cell has reasonable static noise margin value of 149 mV. The circuit performances reveal that UTB-JLFET can be used for sub-5-nm CMOS technology nodes. Index Terms-Junctionless FET (JLFET), ultra-thin body (UTB), germanium.

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Six Sigma has set a new paradigm of excellence in the business environment and is enjoying great popularity. Even though Six Sigma has been in practice in the last two decades, no effort has been made to develop a holistic definition that includes all of the dimensions of Six Sigma. In this paper, the various definitions that exist in the literature have been critically evaluated and a new holistic definition has been proposed. Also, there is a lot of ambiguity in the literature with respect to the origin of Six Sigma. An effort is made to eliminate such confusion by tracking the origin and growth of Six Sigma. Furthermore, in order to facilitate effective implementation, the principles of Six Sigma were identified from the literature. Finally, the misconceptions of Six Sigma are cleared by demystifying its myths.

A silicon junctionless (JL) trench gate-all-around (GAA) nanowire field-effect transistor with an atomically thin channel thickness of 0.65 nm and a very thin oxide with a thickness of 12.3 nm are demonstrated experimentally. Experimental results indicate that this device with a channel thickness of 0.65 nm achieves a sub-threshold slope (SS) of 43 mV/decade, which is the best yet achieved by any reported JLFET. Owing to the atomically thin channel, this device has an extremely high ION/IOFF current ratio of &gt;108. Furthermore, the atomically thin channel GAA JLFET exhibits a low threshold voltage (VTH) variation and negligible drain-induced barrier lowering (DIBL &lt; 0.4 mV/V). The reported device with the thinnest channel has a very high band-to-band tunneling generation rate of 1.2 × 1024/cm2 s when the channel is scaled down to &lt;1 nm, as confirmed by using the 3D quantum transport simulation tool. This quantum tunneling provides a means of achieving an SS value much lower than its fundamental physical limit.

Tunnel FET (TFET) has potential applications in the next generation ultra-low power transistor to substitute the conventional FETs. It can offer very steep inverse subthreshold swing slope to maintain a low leakage current, thus it can be very essential for limiting power consumption in MOSFETs. The carriers in TFET transport from source to channel by the band-to-band tunneling (BTBT) mechanisms. To realize high saturation currents of TFET, it critically depends on the transmission probability, T WKB . In indirect semiconductor, such as Si and Ge, the BTBT model is very crucial for designing and predicting the device performance. In this paper, we employed the nonlocal BTBT model applied to three-dimensional Ge-Si heterojunction TFET with gate length 10 nm compare with Si TFET by including quantum effects simulation. The results show that the Ge-Si TFET outperforms Si TFET because of the lower bandgap and larger tunneling windows. BTBT generation rates of Ge-Si TFET are higher than Si TFET in the on-state condition. The highest BTBT generation rates are located in the source and channel junction and its peaks close to the gate dielectric. Power dissipation is a primary concern for future nanoelectronics devices and switching systems.1 Reducing supply voltage (V DD ), while keeping leakage current very low is very essential for limiting power consumption in MOSFETs.2 As V DD is reduced, the overdrive factor (V DD -V TH ) must be remained high to meet performance requirements. On the other hand, reducing threshold voltage (V TH ) can cause the off-state current (I OFF ) increase exponentially. Therefore, subthreshold swing (SS) must be reduced to maintain a low I OFF . However, conventional MOSFETs cannot provide SS lower than 60 mV/dec at room temperature because of fundamental thermal limits. Charge injection in the MOSFETs occurs by thermionic emission over a potential barrier, is bound by an exponential tail of Fermi statistics. 3,4 In the nanoscale transistor, the cylindrical nanowire is the promising candidate in the ultra-low power vertical devices due to high device density, its negligible trapping and leakage from buffer layer, wrap-gated structure and possibility of very short gate length (below 20 nm).5 Moreover, cylindrical shape tunnel field-effect transistor (TFET) can offer a very steep inverse subthreshold slope for maintain a low leakage current. The TFET is a gated p-i-n transistor with a gate voltage that causes large band bending at the source junction. Hence, the carriers can be transported from source to channel by the band-to-band tunneling (BTBT) mechanism. 6 The carrier injection on the BTBT of electrons from a degenerate p+ source into the channel conduction band causes high-energy carrier are filtered out by the semiconductor bandgap. Thus, steeper subthreshold slopes can be achieved. 3Recent studies have reported many complex fabrication issues of TFETs because of asymmetric doping concentration in source and drain of planar horizontal TFET. For the mature material process like germaniu...

We propose the concept of the electrical junction in a junctionless (JL) field-effect-transistor (FET) to illustrate the transfer characteristics of the JL FET. In this work, nanowire (NW) junctionless poly-Si thin-film transistors are used to demonstrate this conception of the electrical junction. Though the dopant and the dosage of the source, of the drain, and of the channel are exactly the same in the JL FET, the transfer characteristics of the JL FET is similar to these of the conventional inversion-mode FET rather than these of a resistor, which is because of the electrical junction at the boundary of the gate and the drain in the JL FET. The electrical junction helps us to understand the JL FET, and also to explain the superior transfer characteristic of the JL FET with the gated raised S/D (Gout structure) which reveals low drain-induced-barrier-lowering (DIBL) and low breakdown voltage of ion impact ionization.